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revision history 4gb auto-a s4c512m8d3 - 78 ball fbga package revision details date rev 1.0 preliminary datasheet june 2015 alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. reserves the right to change products or specification without notice confidential - 1/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
features jedec standard compliant power supplies: v dd & v ddq = +1.5 v 0.075 v op erating temperature : -40~1 05 c(tc) aec - q100 compliant supports jedec clock jitter specification f ully synchronous operation fast clock rate: 667/800 mhz differential clock, ck & ck # bidirectional di f ferential data strobe - dqs & dqs # 8 internal banks for concurrent operation 8n- bit prefetch architecture pipelined internal architecture precharge & active power down programmable mode & extended mode registers a dditive l atency (al) : 0, cl - 1, cl -2 programmable b urst lengths: 4 , 8 burst type: sequential / interleave output driver impedance cont rol 8192 refresh cycles / 64ms - average refresh period 7.8? @ -40c QtcQ +85c 3.9? @ +85c tcQ +1 0 5c write leveling zq calibration dynamic odt (rtt_nom & rtt_wr) rohs compliant auto refresh and self refresh 78- ball 9 x 1 0.5 x 1.2mm fbga p ackage - pb and halogen free overview the 4g b double-d ata-r ate-3 drams is double data rate architecture to achieve high-s peed operation. it is internally configured as an eight bank dram. the 4gb chip is organized as 64mbit x 8 i/os x 8 bank devices. these synchronous devices achieve high s peed double-da ta-ra te transfer rates of up to 160 0 mb/sec/pin for general applications. the chip is designed to c omply with all key ddr3 dram key features and all of the control and address inputs are synchronized with a pair of externally supplied differential c locks. inputs are latched at the cross point of differential clocks (ck rising and ck# falling). all i/os are s y nchronized with differential dqs pair in a sourc e synchronous fashion. these devices operate with a single 1.5v 0.075v power supply and are available in bga packages . table 1. speed grade information speed grade clock frequency cas latency t rcd (ns) t rp (ns) ddr3 - 1600 800 mhz 5 13. 75 13. 75 table 2. ordering information product part no org temperature max clock (mhz) as4c512 m8d3-12 ban 512 x 8 automotive -40c to 105c 800 package 78 -ball fb g a confidential - 2/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 1. ball assignment (fbga top view) a b c d e 1 2 3 7 8 9 vss vdd vss vssq vddq dq2 vssq dq6 vrefdq vddq nc dq0 dqs dqs# dq4 . tdqs# vss dm/ tdqs vssq dq1 dq3 vdd vss dq7 dq5 vdd vddq vssq vssq vddq f nc vss ras# ck vss nc g odt vdd cas# ck# vdd cke h nc cs# we# a10/ap zq nc j vss ba0 ba2 a15 vrefca vss k a3 a0 a12/bc# ba1 vdd l vss a5 a2 a1 a4 m a7 a9 a11 a6 vdd n vss reset# a13 a14 a8 vdd vdd vss vss confidential - 3/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 2 . block diagram ck# cke cs# ras# cas# we# dll clock buffer command decoder column counter address buffer a10/ap a0-a9 a11 a13-a15 ba0-ba2 ck dqs dqs# dq buffer dm dq7 dq0 ~ odt control signal generator refresh counter data strobe buffer mode register zq cal zqcs zqcl reset# a12/bc# vssq rzq 64m x 8 cell array (bank #0) row decoder column decoder 64m x 8 cell array (bank #1) row decoder column decoder 64m x 8 cell array (bank #2) row decoder column decoder 64m x 8 cell array (bank #3) row decoder column decoder 64m x 8 cell array (bank #4) row decoder column decoder 64m x 8 cell array (bank #5) row decoder column decoder 64m x 8 cell array (bank #6) row decoder column decoder 64m x 8 cell array (bank #7) row decoder column decoder tdqs tdqs# confidential - 4/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 3. state diagram this simplified state diagram is intended to provi de an overview of the possible state transitions and the c ommands to control them. in particular, situations involving more than one bank, the enabling or disabling of on - die termination, and some other events are not captured in full detail . power on automatic sequence command sequence power applied reset procedure initialization reset from any state zqcl zq calibration idle self refresh refreshing sre mrs ref srx zqcl,zqcs active power down activating precharge power down pde pdx act bank activating writing writing reading precharging pdx pde read read read a read a write write read write write a read a pre, prea write a write a pre, prea pre, prea act = active pre = precharge ref = refresh prea = precharge all mrs = mode register set zqcl = zq calibration long read = rd, rds4, rds8 read a = rda, rdas4, rdas8 write = wr, wrs4, wrs8 write a = wra, wras4, wras8 reset = start reset procedure zqcs = zq calibration short pde = enter power-down pdx = exit power-down sre = self-refresh entry srx = self-refresh exit mpr = multi-purpose register reading mrs,mpr, write leveling confidential - 5/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
ball descriptions table 3. ball descriptions symbol type description ck, ck # input differential clock: ck and ck # are driven by the system clock. all sdram input signals are sampled on the crossing of po sitive edge of ck and negative edge of ck#. output (r ead) data is referenced to the crossings of ck and ck# (both directions of crossing). cke input clock enable: cke activates ( high) and deactivates (low ) the ck signal. if cke goes low synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the cke remains low . when all banks are in the idle state, deactivating the clock controls the entry to the power down and self refresh modes. ba0-ba2 input b ank address : ba0-ba2 define to which bank the bankactivate, read, write, or bankprecharge command is being applied. a0 - a1 5 input address inputs: a0 - a1 5 are sampled during the bankactivate command (row address a0 - a1 5 ) and read/write command (column address a0 -a9 with a10 defining auto precharge ). a10/ap input auto - precharge: a10 is sampled during read/write commands to determine whether autoprecharge should be performed to the accessed bank after the read/write operation. (high: autoprecharge; low: no auto precharge). a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). a12/bc# input burst chop: a12/ bc # is sampled during read and write commands to determine if burst chop (on the fly) will be performed. (high - no burst chop; low - burst chopped). cs # input chip select: cs # enables (sampled low) and disables (sampled high) the command decoder . all commands are masked when cs # is sampled high. it is considered part of the command code. ras # input row address strobe: the ras # signal defines the operation co mmands in conjunction with the cas # and we # signals and is latched at the crossing of positive edges of ck and negative edge of ck# . when ras # and cs # are asserted "low" and cas # is asserted "high," either the bankactivate command or the precha rge command is selected by the we # signal. when the we # is asserted "high," the bankactivate command is selected and the bank designated by b a is turned on to the active state. when the we # is asserted "low," the precharge command is selected and the bank designated by b a is switched to the idle state after the precharge operation. cas # input column address strobe: the cas # signal defines the operation commands in conjunction with the ras # a nd we # signals and is latched at the crossing of positive edges of ck and negative edge of ck# . when ras # is held "high" and cs # is asserted "low," the column access is started by asserting cas # "low." then, the read or write co mmand is selected by asserti ng we # high " or low ". we # input write enable: the we # signal defines the operation commands in conjunction with the ras # and cas # signals and is latched at the crossing of positive edges of ck and negative edge of ck# . the we # input is used to select t he bankactivate or precharge command and read or write command. dqs, dqs # input / output bidirectional data strobe: specifies timing for input and output data. read data strobe is edge triggered. write data strobe provides a setup and hold time for data and dm. the data strobes dos is paired with dqs# to provide differential pair signaling to the system during both reads and writes. t dqs t dqs # output termination d ata s trobe: when tdqs is enabled, dm is disabled, and the tdqs and tdqs# balls provide termi nation resistance . dm input data input mask: input data is masked when dm is sampled high during a write cycle. dm has an optional use as tdqs on the x8 . confidential - 6/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
dq0 dq 7 input / output data i/o: the dq0 - dq 7 input and output data are synchronized with positive and negative edges of dqs and dqs#. the i/os are byte - maskable during writes. odt input on die termination: odt (registered high) enables termination resistance internal to the ddr3 sdram. when enabled, odt is applied to each dq, dqs, dqs# , dm/tdqs and tdqs# signal . (when tdqs is enabled via mode register a11=1 in mr1) the odt pin will be ignored if mode - registers, mr1and mr2, are programmed to disable rtt. reset # input active low asynchronous reset: reset is active when reset # is low, and inactive when reset# is high. reset # must be high during normal operation. reset# is a cmos rail to rail signal with dc high and low at 80% and 20% of vdd v dd supply power supply: + 1. 5 v 0.075 v v ss supply ground v ddq supply dq power: + 1. 5 v 0.075 v. v ssq supply dq g round v refca supply reference voltage for ca v refdq supply reference voltage for dq zq supply reference pin for zq calibration. nc - no connect: these pins should be left unconnected. confidential - 7/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
operation mode truth table table 4. truth table (note (1), (2)) command state cke n-1 (3) cke n dm ba0-2 a10 /ap a0 - 9, 11 , 13 - 15 a12/bc# cs # ras # cas # we # bankactivate idle (4) h h x v row address l l h h single bank precharge any h h x v l v v l l h l all banks precharge any h h x v h v v l l h l write (fixed bl8 or bc4) active (4) h h x v l v v l h l l write (bc4, on the fly) active (4) h h x v l v l l h l l write (bl8, on the fly) active (4) h h x v l v h l h l l write with autoprecharge (fixed bl8 or bc4) active (4) h h x v h v v l h l l write with autoprecharge (bc4, on the fly) active (4) h h x v h v l l h l l write with autoprecharge (bl8, on the fly) active (4) h h x v h v h l h l l read (fixed bl8 or bc4) active (4) h h x v l v v l h l h read (bc4, on the fly) active (4) h h x v l v l l h l h read (bl8, on the fly) active (4) h h x v l v h l h l h read with autoprecharge (fixed bl8 or bc4) active (4) h h x v h v v l h l h read with autoprecharge (bc4, on the fly) active (4) h h x v h v l l h l h read with autoprecharge (bl8, on the fly) active (4) h h x v h v h l h l h ( extended ) mode register set idle h h x v op code l l l l no - operation any h h x v v v v l h h h device deselect any h h x x x x x h x x x burst stop active (5) h x x x x x x l h h l refresh idle h h x v v v v l l l h selfrefresh entry idle h l x v v v v l l l h selfrefresh exit idle l h x x x x x h x x x v v v v l h h h power down mode entry idle h l x x x x x h x x x v v v v l h h h power down mode exit any l h x x x x x h x x x v v v v l h h h data in put mask disable active h x l x x x x x x x x data input mask enable (6) active h x h x x x x x x x x zq calibration long idle h h x x h x x l h h l zq calibration short idle h h x x l x x l h h l n ote 1: v=valid data, x=don't care, l=low le vel, h=high level note 2: cken signal is input level when commands are provided. note 3 : cken - 1 signal is input level one clock cycle before the commands are provided. note 4: these are states of bank designated by b a signal. note 5: device state is 4 , and 8 burst operation. note 6: ldm and udm can be enable d respectively. confidential - 8/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
functional description the ddr3 sdram is a high - speed dynamic random access memory internally configured as an eight - bank dram. the ddr3 sdram uses an 8n prefetch architecture to achiev e high speed operation. the 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write operation for the ddr3 sdram consists of a single 8n - bit wide, four clock data transfer at the internal dram core and two corresponding n - bit wide, one - half clock cycle data transfers at the i/o pins. read and write operation to the ddr3 sdram are burst oriented, start at a selected location, and continue for a burst length of eight or a chopped burst of four in a programmed sequence. operation begins with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be activated (ba0 - ba2 select the bank; a0 - a1 5 select the row). the address bit registered coincident with the read or write command are used to select the starting column location for the burst operation, determine if the auto precharge command is to be issued (via a10), and select bc4 or bl8 mode on the fly (via a12) if enabled in the mode register. prior to normal operation, the ddr3 sdram must be powered up and initialized in a predefined manner. the following sections provide detailed infor mation covering device reset and initialization, register definition, command descriptions and device operation. figure 4. reset and initialization sequence at power-on ramping ck# vddq tb tc td te tf tg th ti tj ta reset# ck t cksrx tk t=200? t=500? t dllk t xpr t mrd t mrd t mrd t mod t zqinit mrs note 1 mrs mrs mrs zqcl note 1 valid mr3 mr2 mr1 mr0 valid valid vdd cke ba odt rtt t min =10ns t is t is t is t is static low in case rtt_nom is enabled at time tg, otherwise static high or low don't care time break note 1. from time point h tdi until h tki nop or des commands must be applied between mrs and zqcl commands. command confidential - 9/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l power-up and initialization the following sequ ence is required for power up and initialization . 1. apply power ( reset# is recommended to be maintained below 0.2 x vdd, all other inputs may be undefined). reset# needs to be maintained for minimum 200 u s with stable power. cke is pulled low anytime b efore reset# being de- asser t ed (min. time 10ns). the power voltage ramp time between 300mv to vddmin must be no greater than 200ms; and during the ramp, vdd>vddq and (vdd - vddq) <0.3 volts. - vdd and vddq are driven from a single power converter output, and - the voltage levels on all pins other than vdd, vddq, vss, vssq must be less than or equal to vddq and vdd on one side and must be larger than or equal to vssq and vss on the other side. in addition, vtt is limited to 0.95v max once power ramp is finished, and - vref tracks vddq/2. or - apply vdd without any slope reversal before or at the same time as vddq. - apply vddq without any slope reversal before or at the same time as vtt & vref. - the voltage levels on all pins other than vdd, vddq, vss, vssq mu st be less than or equal to vddq an d vdd on one side and must be larger than or equal to vssq and vss on the other side. 2. after reset# is de - asserted, wait for another 500us until cke become active. during this time, the dram will start internal state initialization; this will be done independently of external clocks. 3. clock (ck, ck# ) need to be started and stabilized for at least 10ns or 5tck (which is larger) before cke goes active. since cke is a synchronous signal, the corresponding set up time to c lock (tis) must be meeting. also a nop or deselect command must be registered (with tis set up time to clock) before cke goes active. once the cke registered ?igh?after reset, cke needs to be continuously registered ?igh?until the initialization sequence is finished, including expiration of tdllk and tzqinit. 4. the ddr3 dram will keep its on - die termination in high impedance state as long as reset# is asserted. further, the dram keeps its on - die termination in high impedance state after reset# deassert ion until cke is registered high. the odt input signal may be in undefined state until tis before cke is registered high. when cke is registered high, the odt input signal may be statically held at either low or high. if rtt_nom is to be enabled in mr1, th e odt input signal must be statically held low. in all cases, the odt input signal remains static until the power up initialization sequence is finished, including the expiration of tdllk and tzqinit. 5. after cke being registered high, wait minimum of res et cke exit time, txpr, before issuing the first mrs command to load mode register. ( txpr =max (txs, 5tck) ) 6. issue mrs command to load mr2 with all application settings. (to issue mrs command for mr2, provide low to ba0 and ba2, high to ba1) 7. issue m rs c ommand to load mr3 with all application settings. (to issue mrs command for mr3, provide low to ba2, high to ba0 and ba1) 8. issue mrs c ommand to load mr1 with all application settings and dll enabled. (to issue dll enable command, provide low to a0, high to ba0 and low to ba1 and ba2) 9. issue mrs command to load mr0 with all application settings and dll reset. (to issue dll r eset command p rovide ?igh?to a8 and ?ow?to ba0 - ba2) 10 . issue zqcl command to starting zq calibration. 11. wait fo r both tdllk and tzqinit completed. 12. the ddr3 sdram is now ready for normal operation. confidential - 10/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l reset procedure at stable power the following sequence is required for reset at no power interruption initialization. 1. asserted reset below 0.2*vdd anytime when reset is needed (all other inputs may be undefined). reset needs to be maintained for minimum 100ns. cke is pulled low before reset bein g de - asserted (min. time 10ns). 2. follow power - up initialization sequence step 2 to 11. 3. the reset s equence is now completed. ddr3 sdram is ready for normal operation. figure 5. reset procedure at power stable condition ck# vddq tb tc td te tf tg th ti tj ta reset# ck t cksrx tk t=100ns t=500? t dllk t xpr t mrd t mrd t mrd t mod t zqinit mrs note 1 mrs mrs mrs zqcl note 1 valid mr3 mr2 mr1 mr0 valid valid vdd command cke ba odt rtt t is t is t is t is static low in case rtt_nom is enabled at time tg, otherwise static high or low don't care time break note 1. from time point h td i until h tk i nop or des commands must be applied between mrs and zqcl commands. t min =10ns confidential - 11/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
register definition l programming the mode registers for application flexibility, various functions, features, and modes are programmable in four mode registers, provided by the ddr3 sdram, as user defined variables and they must be programmed via a mode register set (mrs) command. as the default values of the mode registers are not defined, contents of mode registers must be fully initialized and/or re - initialized, i.e. , written, after power up and/or reset for proper operation. also the contents of the mode registers can be altered by re - executing the mrs command during normal operation. when programming the mode registers, even if the user chooses to modify only a sub - set of the mrs fields, all address fields within the accessed mode register must be redefined when the mrs command is issued. mrs command and dll reset do not affect array contents, which mean these commands can be executed any time after power - up without affecting the array contents. the mode register set command cycle time, tmrd is required to complete the write operation to the mode register and is the minimum time required between two mrs commands shown in figure of tmrd timing. figure 6. tmrd timing t1 t2 ta0 ta1 tb0 tb1 tb2 tc0 tc1 t0 tc2 valid t mrd odtloff + 1 don't care time break valid valid valid mrs nop/des nop/des mrs nop/des nop/des valid valid valid valid valid valid valid valid valid valid valid valid valid old settings updating settings valid valid valid valid valid valid valid valid valid valid valid valid valid t mod new settings rtt_nom enabled prior and/or after mrs command rtt_nom disabled prior and after mrs command ck# address ck command cke settings odt odt confidential - 12/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
the mrs command to non - mrs command delay, tmod, is require for the dram to update the features except dll reset, and is the minimum time required from an m rs command to a non - mrs command excluding nop and des shown in figure of tmod timing. figure 7. tmod timing ck# t1 t2 ta0 ta1 ta2 ta3 ta4 tb0 tb1 t0 address ck tb2 valid command cke settings odt odt odtloff + 1 don't care time break valid valid valid mrs nop/des nop/des nop/des nop/des nop/des valid valid valid valid valid valid valid valid valid valid valid valid valid old settings updating settings valid valid valid valid valid valid valid valid valid valid valid valid valid t mod new settings rtt_nom enabled prior and/or after mrs command rtt_nom disabled prior and after mrs command the mode register contents can be changed using the same command and timing requirements during normal operation as long as the dram is in idle state, i.e. , all banks are in the precharged state with trp satisfied, all data bursts are completed and cke is high prior to writing into the mode register. the mode registers are divided into various fields depending on the functionality and/or modes. confidential - 13/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l mode register mr0 the mode - register mr0 stores data for controlling various operating modes of ddr3 sdram. it controls burst length, read burst type, cas latency, test mode, dll reset, wr, and dll control for precharge pow er - down, which include various vendor specific options to make ddr3 dram useful for various applications. the mode register is written by asserting low on cs#, ras#, cas#, we#, ba0, ba1, and ba2, while controlling the states of address pins according to th e following figure. table 5. mode register bitmap b a2 ba1 b a0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 *1 0 0 0 *1 0 *1 0 *1 ppd wr dll tm cas latency rbt 0 bl mode register (0) ba1 ba0 mrs mode a7 mode a3 read burst type a1 a0 bl 0 0 mr0 0 normal 0 nibble sequential 0 0 8 (fixed) 0 1 mr1 1 test 1 interleave 0 1 bc4 or 8 (on the fly) 1 0 mr2 1 0 bc4 (fixed) 1 1 mr3 1 1 reserved a11 a10 a9 wr (cycles) a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 5 *2 0 0 0 reserved 0 1 0 6 *2 0 0 1 5 0 1 1 7 *2 0 1 0 6 1 0 0 8 *2 0 1 1 7 1 0 1 10 *2 1 0 0 8 1 1 0 12 *2 1 0 1 9 1 1 1 14 *2 1 1 0 10 1 1 1 11 a12 dll control for precharge pd 0 slow exit (dll off) a8 dll reset 1 fast exit (dll on) 0 no 1 yes note 1: r eserved for future use and must be set to 0 when programming the mr. note 2: wr (write recovery for autoprecharge) min in clock cycle s is calculated by dividing twr ( ns) by tck ( ns) and rounding up to the next integer wr min [cycles] =roundup (twr / tck). the value in the mode register must be programmed to be equal or larger than wrmin. the programmed wr value is used with trp to determine tdal. confidential - 14/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
- burst length, type, and order accesses within a given burst may be programmed to sequential or interleaved order. the burst type is selected via bit a3 as shown in the mr0 definition as above figure. the ordering of access within a burst is determined by the burst length, burst type, and the starting column address. the burst length is defined by bits a0 - a1. burst lengths options include fix bc4, fixed bl8, and on the fly which allow bc4 or bl8 to be selected coincident with th e registration of a read or write command via a12/ bc# table 6. burst type and burst order burst length read write starting column address sequential a3=0 interleave a3=1 note a2 a1 a0 4 chop read 0 0 0 0, 1, 2, 3, t, t, t, t 0, 1, 2, 3, t, t, t, t 1, 2, 3 0 0 1 1, 2, 3, 0, t, t, t, t 1, 0, 3, 2, t, t, t, t 0 1 0 2, 3, 0, 1, t, t, t, t 2, 3, 0, 1, t, t, t, t 0 1 1 3, 0, 1, 2, t, t, t, t 3, 2, 1, 0, t, t, t, t 1 0 0 4, 5, 6, 7, t, t, t, t 4, 5, 6, 7, t, t, t, t 1 0 1 5, 6, 7, 4, t, t, t, t 5, 4, 7, 6, t, t, t, t 1 1 0 6, 7, 4, 5, t, t, t, t 6, 7, 4, 5, t, t, t, t 1 1 1 7, 4, 5, 6, t, t, t, t 7, 6, 5, 4, t, t, t, t write 0 v v 0, 1, 2, 3, x, x, x, x 0, 1, 2, 3, x, x, x, x 1, 2, 4, 5 1 v v 4, 5, 6, 7, x, x, x, x 4, 5, 6, 7, x, x, x, x 8 read 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 2 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4 , 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 write v v v 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 2, 4 note 1: in case of burst length being fixed to 4 by mr0 setting, the internal write operation starts two clock cycles earlier than for the bl8 mode. this means that the starting point for twr and twtr will be pulled in by two clocks . in case of burst length being selected on - the - fly via a12/bc#, the internal write operation starts at the same point in time like a burst of 8 write operation. this means that during on - the - fly control, the starting point for twr and twtr will not be pul led in by two clocks. note 2: 0~ 7 bit number is value of ca[2:0] that causes this bit to be the first read during a burst. note 3: t: output driver for data and strobes are in high impedance . note 4: v: a valid logic level (0 or 1), but respective buffe r input ignores level on input pins. note 5: x: dont care. - cas latency the cas latency is defined by mr0 (bit a 2, a4 ~a 6 ) as shown in the mr0 definition figure. cas latency is the delay, in clock cycles, between the internal read command and the availa bility of the first bit of output data. ddr3 sdram does not su pport any half clock latencies. the overall read latency (rl) is defined as additive latency (al) + cas latency (cl); rl = al + cl. - test mode the normal operating mode is selected by mr0 (bit 7=0) and all other bits set to the desired values shown in the mr0 definition figure. programming bit a7 to a 1 places the ddr3 sdram into a test mode that is only used by the dram manufacturer and should not be used. no operations or functionality is gu aranteed if a7=1. - dll reset the dll reset bit is self - clearing, meaning it returns back to the value of 0 after the dll reset function has been issued. once the dll is enabled, a subsequent dll reset should be applied. anytime the dll reset function i s used, tdllk must be met before any functions that require the dll can be used (i.e. read commands or odt synchronous operations.) confidential - 15/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
- write recovery the programmed wr value mr0 (bits a9, a10, and a11) is used for the auto precharge feature along with trp to determine tdal. wr (write recovery for auto - precharge) min in clock cycles is calculated by dividing twr (ns) by tck (ns) and rounding up to the next integer: wr min [cycles] = roundup (twr [ns]/tck [ns]). the wr must be programmed to be equal or large r than twr (min). - precharge pd dll mr0 (bit a12) is used to select the dll usage during precharge power - down mode. when mr0 (a12=0), or slow - exit, the dll is frozen after entering precharge power - down (for potential power savings) and upon exit requires txpdll to be met prior to the next valid command. when mr0 (a12=1), or fast - exit, the dll is maintained after entering precharge power - down and upon exiting power - down requires txp to be met prior to the next valid command. l mode register mr1 the mod e register mr1 stores the data for enabling or disabling the dll, output strength, rtt_nom impedance, additive latency, write leveling enable , tdqs enable and qoff. the mode register 1 is written by asserting low on cs# , ras# , cas# , we#, high on ba0 and lo w on ba1 and ba2, while controlling the states of address pins according to the following figure. table 7. extended mode register emr (1) bitmap b a2 ba1 b a0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 *1 0 1 0 *1 0 *1 0 *1 qoff tdqs 0 *1 rtt_nom 0 *1 level rtt_nom d.i.c al rtt_nom d.i.c dll mode register (1) ba1 ba0 mrs mode a4 a3 additive latency a0 dll enable 0 0 mr0 0 0 0 (al disabled) 0 enable 0 1 mr1 0 1 cl 1 1 disable 1 0 mr 2 1 0 cl 2 1 1 mr 3 1 1 reserved a12 qoff *2 a9 a6 a2 rtt_nom *3 0 output buffer enabled 1 o utput buffer disabled 0 0 0 rtt_nom disabled 0 0 1 rzq/4 a11 tdqs a7 write leveling enable 0 1 0 rzq/2 0 disable 0 disabled 0 1 1 rzq/6 1 enable 1 enabled 1 0 0 rzq/12 *4 note: rzq = 240 1 0 1 rzq/8 *4 a5 a1 output driver impedance control 1 1 0 reserved 0 0 rzq/6 1 1 1 reserved 0 1 rzq/7 note: rzq = 240 1 0 reserved 1 1 reser ved note 1: reserved for future use and must be set to 0 when programming the mr. note 2: outputs disabled - dqs, dqss, dqs#s. note 3: in write leveling mode (mr1 [bit7] = 1) with mr1 [bit12] =1, all rtt_nom s ettings are allowed; in write levelin g mode (mr1 [bit7] = 1) with mr1 [bit12]=0, only rtt_nom settings of rzq/2, rzq/4 and rzq/6 are allowed. note 4: if rtt_nom is used during writes, only the values rzq/2, rzq/4 and rzq/6 are allowed. confidential - 16/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
- dll enable/disable the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon returning to normal operation after having the dll disabled. during normal operation (dll - on) with mr1 (a0=0), the dll is automatically disabled when entering self - refresh operatio n and is automatically re - enable upon exit of self - refresh operation. any time the dll is enabled and subsequently reset, tdllk clock cycles must occur before a read or synchronous odt command can be issued to allow time for the internal clock to be synchr onized with the external clock. failing to wait for synchronization to occur may result in a violation of the tdqsck, taon, or taof parameters. during tdllk, cke must continuously be registered high. ddr3 sdram does not require dll for any write operation, expect when rtt_wr is enabled and the dll is required for proper odt operation. for more detailed information on dll disable operation are described in dll - off mode. the direct odt feature is not supported during dll - off mode. the on - die termination resis tors must be disabled by continuously registering the odt pin low and/or by programming the rtt_nom bits mr1{a9,a6,a2} to {0,0,0} via a mode register set command during dll - off mode. the dynamic odt feature is not supported at dll - off mode. user must use m rs command to set rtt_wr, mr2 {a10, a9} = {0, 0}, to disable dynamic odt externally - output driver impedance control the outpu t driver impedance of the ddr3 sdram device is selected by mr1 (bit a1 and a5) as shown in mr1 definition figure. - odt rtt values ddr3 sdram is capable of providing two different termination values (rtt_nom and rtt_wr). the nominal termination value rtt_nom is programmable in mr1. a separate value (rtt_wr) may be programmable in mr2 to enable a unique rtt value when odt is enable d during writes. the rtt_wr value can be applied during writes even when rtt_nom is disabled. - additive latency (al) additive latency (al) operation is supported to make command and data bus efficient for sustainable bandwidth in ddr3 sdram. in this oper ation, the ddr3 sdram allows a read or write command (either with or without auto - precharge) to be issued immediately after the active command. the command is held for the time of the additive latency (al) before it is issued inside the device. the read la tency (rl) is controlled by the sum of the al and cas latency (cl) register settings. write latency (wl) is controlled by the sum of the al and cas write latency (cwl) register settings. a summary of the al register options are shown in mr. - write leveli ng for better signal integrity, ddr3 memory module adopted fly - by topology for the commands, addresses, control signals, and clocks. the fly - by topology has benefits from reducing number of stubs and their length but in other aspect, causes flight time ske w between clock and strobe at every dram on dimm. it makes difficult for the controller to maintain tdqss, tdss, and tdsh specification. therefore, the controller should support write leveling in ddr3 sdram to compensate for skew. - output disable the d dr3 sdram outputs maybe enable/disabled by mr1 (bit 12) as shown in mr1 definition. when this feature is enabled (a12=1) all output pins (dqs, dqs, dqs# , etc.) are disconnected from the device removing any loading of the output drivers. this feature may be useful when measuring modules power for example. for normal operation a12 should be set to 0. - tdqs enable tdqs (termination data strobe) is a feature of ddr3 sdram that provides additional termination resistance outputs that may be useful in some sys tem configurations. in contrast to the rdqs function of ddr2 sdram, tdqs provides the termination resistance function only. the data strobe function of rdqs is not provided by tdqs. the tdqs and dm functions share the same pin. when the tdqs function is en abled via the mode register, the dm function is not supported. when the tdqs function is disabled, the dm function is provided and the tdqs# pin is not used. the tdqs function is available in x8 ddr3 sdram only confidential - 17/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l mode register mr2 the mode register mr2 s tores the data for controlling refresh related features, rtt_wr impedance, and cas write latency. the mode register 2 is written by asserting low on cs# , ras# , cas# , we#, high on ba1 and low on ba0 and ba2, while controlling the states of address pins acco rding to the table below. table 8. extended mode register emr (2) bitmap b a2 ba1 b a0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 *1 1 0 0 *1 rtt_wr 0 *1 srt asr cwl pasr mode register (2) ba1 ba0 mr s mode a6 auto self - refresh (asr) 0 0 mr0 0 manual sr reference (srt) 0 1 mr 1 1 asr enable (optional) 1 0 mr2 1 1 mr3 a10 a9 rtt_wr *2 a2 a1 a0 partial array self - refresh (optional) 0 0 dynamic odt off (write does not affect rtt value) 0 1 rzq/4 0 0 0 full array 1 0 rzq/2 0 0 1 halfarray (ba[2:0]=000,001,010,&011) 1 1 reserved 0 1 0 quarter array (ba[2:0]=000,&001) 0 1 1 1/8 th array (ba[2:0]=000) 1 0 0 3/4 array (ba[2:0]=0 10,011,100.101,110,&111) 1 0 1 halfarray (ba[2:0]=100,101,110,&111) 1 1 0 quarter array (ba[2:0]=110,&111) 1 1 1 1/8 th array (ba[2:0]=111) a7 self - refresh temperature (srt) range a5 a4 a3 cas write latency (cwl ) 0 normal operating temperature range 0 0 0 5 (tck(avg) R 2.5ns) 1 extended (optional) operating temperature range 0 0 1 6 (2.5ns tck(avg) R 1.875ns) 0 1 0 7 (1.875ns tck(avg) R 1.5ns) 0 1 1 8 (1.5ns tck(avg) R 1.25ns) 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved note 1: ba2 and a8, a 11~ a1 5 are rfu and must be programmed to 0 during mrs . note 2: the rtt_wr value can be applied during writes even when rtt_nom is disabled. during write leveling, dynamic odt is not available. confidential - 18/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
- partial array self-refresh (pasr) optional in ddr3 sdram: users should refer to the dram supplier data sheet and/or the dimm spd to determine if ddr3 sdram devices support the following options or requirements referred to in this material. if pasr (partial array self - refresh) is en abled, data located in areas of the array beyond the specified address range will be lost if self - refresh is entered. data integrity will be maintained if trefi conditions are met and no self - refresh command is issued. - cas write latency (cwl) the cas wr ite latency is defined by mr2 (bits a3 - a5) shown in mr2. cas write latency is the delay, in clock cycles, between the internal write command and the availability of the first bit of input data. ddr3 dram does not support any half clock latencies. the overa ll write latency (wl) is defined as additive latency (al) + cas write latency (cwl); wl=al+cwl. for more information on the supported cwl and al settings based on the operating clock frequency, refer to ?tandard speed bins. for detailed write operation r efer to write operation. - auto self-refresh (asr) and self-refresh temperature (srt) ddr3 sdram must support self - refresh operation at all supported temperatures. applications requiring self - refresh operation in the extended temperature range must use the asr function or program the srt bit appropriately. optional in ddr3 sdram: users should refer to the dram supplier data sheet and/or the dimm spd to determine if ddr3 sdram devices support the following options or requirements referred to in this mate rial. for more details refer to ?xtended temperature usage? ddr3 sdrams must support self - refresh operation at all supported temperatures. applications requiring self - refresh operation in the extended temperature range must use the optional asr function or program the srt bit appropriately. - dynamic odt (rtt_wr) ddr3 sdram introduces a new feature dynamic odt. in certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the ddr3 sdram can be changed without issuing an mrs command. mr2 register locations a9 and a10 configure the dynamic odt settings. ddr3 sdram introduces a new feature dynamic odt. in certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the ddr3 sdram can be changed without issuing an mrs command. mr2 register locations a9 and a10 configure the dynamic odt settings. in write leveling mode, only rtt_nom is available. for details on dyn amic odt operation, refer to dynamic odt. confidential - 19/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l mode register mr3 the mode register mr3 controls multi - purpose registers. the mode register 3 is written by asserting low on cs# , ras# , cas# , we# , high on ba1 and ba0, and low on ba2 while controlling the state s of address pins according to the table below table 9. extended mode register emr (3) bitmap b a2 ba1 b a0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 *1 1 1 0 *1 mpr mpr loc mode register (3) ba1 ba0 m rs mode a2 mpr a1 a0 mpr location 0 0 mr0 0 normal operation *3 0 0 predefined pattern *2 0 1 mr1 1 dataflow from mpr 0 1 rfu 1 0 mr2 1 0 rfu 1 1 mr3 1 1 rfu note 1: ba2, a3 - a1 5 are rfu and must be programmed to 0 during mrs. note 2: the predefined pattern will be used for read synchronization. note 3: when mpr control is set for normal operation (mr3 a [2] = 0) then mr3 a[1:0] will be ignored. confidential - 20/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
table 10. absolute maximum dc ratings symbol parameter values unit note v dd voltage on vdd pin relative to vss - 0.4 ~ 1. 8 v 1,3 v ddq voltage on vddq pin relative to vss - 0. 4 ~ 1. 8 v 1,3 v in , v out voltage on any pin relative to vss - 0.4 ~ 1. 8 v 1 t stg storage te mperature -5 5~100 c 1, 2 n ote1 : stresses greater t han thos e list ed under "absolut e maximum ratings" m ay caus e permanent dam age t o the device.this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of t his specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. note2: storage temperature is the case surface temperature on the center/top side of the dram. note3: vdd and vddq must be within 300mv of each other at all times; and vref must be not greater than 0.6vddq, when vdd and vddq are less than 500mv; vref may be equal to or less than 300mv. table 1 1. temperature range symbol parameter values unit note t oper automotive t emperature range -4 0~10 5 c 1-4 n ote 1: operating temperature is the case surface temperature on center/top of the dram. note2: the operating temperatu r e range is the temperature where all dram specification will be supported. outside of this temper atur e range, even if it is still withi n t he limit of stress condition, som e deviati on on porti on of operating specification may be required. during oper ation, the dram cas e temperatur e must be maintained between 0-8 5c under all other specification parameter. supporting 0 - 85 ? with full jedec ac & dc s pecifications. note3: some applications require operation of the dram in the extended temperature range between 85 c and 95 c case temperature. full specifications are guaranteed in this range, but the following additional apply. a) refresh commands must be doubled in frequency, therefore, reducing the refresh interval trefi to 3.9us. it is also possible to specify a component with 1x refresh (trefi to 7.8us) in the extended temperature range. b) if self - refresh operation is required in the extended temperature range, then it is mandatory to either use the manual self - refresh mode with extended temperature range capability (mr2 a6=0 and mr2 a7=1) or enable the optional auto self - refre sh mode (mr2 a6=1 and mr2 a7=0). note4: during automotive temperature operation range, the dram case temperature must be maintained between - 40c~105c under all operating conditions. table 12. recommended dc operating conditions symbol parameter min. ty p. max. unit note v dd power s upply v oltage 1.425 1. 5 1.575 v 1,2 v ddq power s upply v oltage for output 1.425 1. 5 1.575 v 1,2 note1 : under all conditions vddq must be less than or equal to vdd. note2 : vddq tracks with vdd. ac parameters are measured with vdd and vddq tied together. confidential - 21/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
table 13. single-ended ac and dc input levels for command and address symbol parameter - 12 unit note min. max. v ih .ca(dc100) dc input logic high v ref +0.1 v dd v 1,5 v il .ca(dc100) dc input logic lo w v ss v ref - 0.1 v 1,6 v ih .ca(ac175) ac input logic high v ref + 0.175 - v 1,2 v il .ca(ac175) ac input logic low - v ref - 0.175 v 1,2 v ih .ca(ac150) ac input logic high v ref + 0.15 - v 1,2 v il .ca(ac150) ac input logic low - v ref - 0.15 v 1,2 v refca (dc) r eference voltage for add, cmd inputs 0.49xv dd 0.51xv dd v 3,4 note 1 : for input only pins except reset#. vref = vrefca(dc). note 2 : see overshoot and undershoot specifications . note 3 : the ac peak noise on vref may not allow vref to deviate from vrefca(dc) by more than +/ - 1% vdd . not e 4 : for reference: approx. vdd/2 +/ - 15 mv. note 5 : vih(dc) is used as a simplified symbol for vih.ca(dc100) note 6 : vil(dc) is used as a simplified symbol for vil.ca(dc100) note 7 : vih(ac) is used as a simplified symbol for vih.ca(ac175), vih.ca(ac150) a nd vih.ca(ac175) value is used when vref + 0.175v is referenced, vih.ca(ac150) value is used when vref + 0.150v is referenced . note 8 : vil(ac) is used as a simplified symbol for vil.ca(ac175), vil.ca(ac150) and vil.ca(ac175) value is used when vref - 0.175 v is referenced, vil.ca(ac150) value is used when vref - 0.150v is referenced . table 14. single-ended ac and dc input levels for dq and dm symbol parameter - 12 unit note min. max. v ih . dq (dc100) dc input logic high v ref +0.1 v dd v 1,5 v il . dq (dc100) dc input logic lo w v ss v ref - 0.1 v 1,6 v ih . dq (ac150) ac input logic high v ref + 0.15 - v 1,2 v il . dq (ac150) ac input logic low - v ref - 0.15 v 1,2 v refdq (dc) r eference voltage for dq, dm inputs 0.49x v dd 0.51x v dd v 3,4 note 1 : vref = vrefdq(dc). note 2 : see ?vershoot and undershoot specifications? note 3 : the ac peak noise on vref may not allow vref to deviate from vrefdq(dc) by more than +/ - 1% vdd . note 4 : for reference: approx. vdd/2 +/ - 15 mv. note 5 : vih(dc) is used as a simplified symbol for vih.dq(dc1 00) note 6 : vil(dc) is used as a simplified symbol for vil.dq(dc100) note 7 : vih(ac) is used as a simplified symbol for vih.dq(ac150) and vih.dq(ac150) value is used when vref + 0.150v is referenced . note 8 : vil(ac) is used as a simplified symbol for vil.d q(ac150) and vil.dq(ac150) value is used when vref - 0.150v is referenced . confidential - 22/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
table 15. differential ac and dc input levels symbol parameter min. max. unit note v ih diff differential input high 0.2 - v 1 , 3 v il diff differential input logic low - - 0.2 v 1 , 3 v ih diff( ac ) differential input high ac 2 x (v ih ( ac ) - v ref ) - v 2 , 3 v il diff( ac ) differential input low ac - 2 x (v il ( ac ) - v ref ) v 2 , 3 note 1 : used to define a differential signal slew - rate. note 2 : for ck - ck# use vih/vil(ac) of add/cmd and vref ca; for dqs, dqs# use vih/vil(ac) of dqs and vrefdq; if a reduced ac - high or ac - low level is used for a signal group, then the reduced level applies also here. note 3 : these values are not defined; however, the single - ended signals ck, ck#, dqs, dqs# need to be within the respective limits (vih(dc) max, vil(dc)min) for single - ended signals as well as the limitations for overshoot and undershoot. table 16. capacitance (v dd = 1. 5 v, f = 1mhz, t oper = 25 c) symbol parameter ddr3 - 1600 unit note min. max . c io input/output capacitance , (dq, dm, dqs, dqs# , t dqs, t dqs#) 1. 5 2.3 pf 1, 2, 3 c ck input capacitance, ck and ck# 0.8 1.4 pf 2, 3 c dck input capacitance delta, ck and ck# 0 0.15 pf 2, 3, 4 c ddqs input/output capacitance delta, dqs and dqs# 0 0.15 pf 2, 3, 5 c i input capacitance, (ctrl, add, cmd input - only pins) 0.75 1.3 pf 2, 3, 6 c di_ctrl input capacitance delta, (all ctrl input - only pins ) - 0.4 0.2 pf 2, 3, 7, 8 c di_add_cmd input capacitance delta, (all add , cmd input - only pins) - 0.4 0.4 pf 2 , 3, 9, 10 c dio input/output capacitance delta, (dq, dm, dqs, dqs# , t dqs, t dqs#) - 0.5 0.3 pf 2, 3, 11 c zq input/output capacitance of zq pin - 3 pf 2, 3, 12 note 1 : although the dm , tdqs and tdqs# pins have different functions, the loading matches dq and dqs . note 2 : this parameter is not subject to production test. it is verified by design and characterization. vdd=vddq=1.5v, vbias=vdd/2 and ondie termination off. note 3 : this parameter applies to monolithic devices only; stacked/dual - die devices are not covered here . note 4 : absolute value of cck - cck# . note 5 : absolute value of cio(dqs) - cio(dqs#) . note 6 : ci applies to odt, cs#, cke, a0 - a1 5 , ba0 - ba2, ras#, cas#, we#. note 7 : cdi_ctrl applies to odt, cs# and cke . note 8 : cdi_ctrl=ci(ctrl) - 0.5*(ci(ck)+c i(c k#)) . note 9 : cdi_add_cmd applies to a0 - a1 2 , ba0 - ba2, ras#, cas# and we# . note 10 : cdi_ add_cmd=ci(add_cmd) - 0.5*(ci(ck)+ci(c k#)) . note 11 : cdio=cio(dq,dm) - 0.5*(cio(dqs)+cio(dqs#)) . note 12 : maximum external load capacitance on zq pin: 5 pf. confidential - 23/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
table 17. idd specification parameters and test conditions (v dd = 1.5 v 0.075 v, t oper = -4 0~10 5 c) parameter & test condition symbol - 12 unit max. operating one bank active - precharge current cke: high; external clock: on; bl: 8 *1 ; al: 0; cs# : high betwe en act and pre; command, address, bank address inputs: partially toggling; data io: mid - level; dm :stable at 0; bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,...; output buffer and rtt: enabled in mode registers *2 ; odt signal: stable at 0. i dd0 84 ma operating one bank active - read - precharge current cke: high; external clock: on; bl: 8 *1, 7 ; al: 0; cs# : high between act, rd and pre; command, address, bank address inputs, data io: partially toggling; dm :stable at 0; bank activity: cycling w ith one bank active at a time: 0,0,1,1,2,2,...; output buffer and rtt: enabled in mode registers *2 ; odt signal: stable at 0 . i dd1 99 ma precharge standby current cke : high; external clock: on; bl: 8 *1 ; al: 0; cs# : stable at 1; command, address, bank addre ss inputs: partially toggling; data io: mid - level; dm :stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers *2 ; odt signal: stable at 0 . i dd2n 60 ma precharge power - down current slow exit cke: low; external clock: o n; bl: 8 *1 ; al: 0; cs# : stable at 1; command, address, bank address inputs: stable at 0; data io: mid - level; dm :stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers *2 ; odt signal: stable at 0; pecharge power down m ode: slow exit . *3 i dd2p0 22 ma precharge power - down current fast exit cke: low; external clock: on; bl: 8 *1 ; al: 0; cs# : stable at 1; command, address, bank address inputs: stable at 0; data io: mid - level; dm :stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers *2 ; odt signal: stable at 0; pecharge power down mode : fast exit . *3 i dd2p1 45 ma precharge quiet standby current cke : high; external clock: on; bl: 8 *1 ; al: 0; cs# : stable at 1; command, address, bank addres s inputs: stable at 0; data io: mid - level; dm :stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers *2 ; odt signal: stable at 0 . i dd2q 60 ma active standby current cke : high; external clock: on; bl: 8 *1 ; al: 0; cs# : stable at 1; command, address, bank address inputs: partially toggling; data io: mid - level; dm :stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers *2 ; odt signal: stable at 0 . i dd3n 69 ma active power - down current ck e: low; external clock: on; bl: 8 *1 ; al: 0; cs# : stable at 1; command, address, bank address inputs: stable at 0; data io: mid - level; dm :stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers *2 ; odt signal: stable at 0 i dd3p 54 ma operating burst read current cke: high; external clock: on; bl: 8 *1, 7 ; al: 0; cs# : high between rd; command, address, bank address inputs: partially toggling; dm :stable at 0; bank activity: all banks open, rd commands cycling through banks: 0 ,0,1,1,2,2,...; tput buffer and rtt: enabled in mode registers *2 ; odt signal: stable at 0 . i dd4r 225 ma operating burst write current cke: high; external clock: on; bl: 8 *1 ; al: 0; cs# : high between wr; command, address, bank address inputs: partially toggling; dm: stable at 0; bank activity: all banks open . output buffer and rtt: enabled in mode registers *2 ; odt signal: stable at high . i dd4w 198 ma confidential - 24/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
burst refresh current cke: high; external clock: on; bl: 8 *1 ; al: 0; cs# : high between t ref; command, ad dress, bank address inputs: partially toggling; data io: mid - level; dm :stable at 0; bank activity: ref command every t rfc; output buffer and rtt: enabled in mode registers *2 ; odt signal: stable at 0 . i dd5b 264 ma self refresh current: auto self - refresh (a sr) : disabled *4 ; self - refresh temperature range (srt): normal *5 ; cke: low; external clock: off; ck and ck#: low; bl: 8 *1 ; al: 0; cs#, command, address, bank address, data io: mid - level; dm :stable at 0; bank activity: self - refresh operation; output buffer an d rtt: enabled in mode registers *2 ; odt signal: mid - level i dd6 56 ma operating bank interleave read current cke: high; external clock: on; bl: 8 *1, 7 ; al: cl - 1; cs# : high between act and rda; command, address, bank address inputs: partially toggling; dm :stable at 0; output buffer and rtt: enabled in mode registers *2 ; odt signal: stable at 0 . i dd7 324 ma reset low current reset: low; external clock: off; ck and ck#: low; cke: floating; cs# , command, address, bank address, data io: floating; odt signal: flo ating reset low current reading is valid once power is stable and reset has been low for at least 1ms. i dd8 24 ma note 1 : burst length: bl8 fixed by mrs: set mr0 a[1,0]=00b note 2 : output buffer enable: set mr1 a[12] = 0b; set mr1 a[5,1] = 01b; rtt_nom en able: set mr1 a[9,6,2] = 011b; rtt_wr enable: set mr2 a[10,9] = 10b note 3 : pecharge power down mode: set mr0 a12=0b for slow exit or mr0 a12=1b for fast exit note 4 : auto self - refresh (asr): set mr2 a6 = 0b to disable or 1b to enable feature note 5 : self - refresh temperature range (srt): set mr2 a7=0b for normal or 1b for extended temperature range note 6 : refer to dram supplier data sheet and/or dimm spd to determine if optional features or requirements are supported by ddr3 sdram device note 7 : read burst type: nibble sequential, set mr0 a[3] = 0b confidential - 25/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
table 18. electrical characteristics and recommended a.c. operating conditions (v dd = 1.5v 0.075 v , t oper = -4 0~10 5 c) symbol parameter - 12 unit min. max. t aa internal read command to fi rst data 13.75 20 ns t rcd act to internal read or write delay time 13.75 - ns t rp pre command period 13.75 - ns t rc act to act or ref command period 4 8.75 - ns t ras active to precharge command period 35 9 * t refi ns t ck(avg) average clock period cl=7 , cwl=6 1.875 <2.5 ns cl=8, cwl= 6 1.875 <2.5 ns cl=9, cwl=7 1.5 <1.875 ns cl=10, cwl= 7 1.5 <1.875 ns cl=1 1 , cwl= 8 1.25 <1.5 ns t ck (dll_off) minimum clock cycle time (dll off mode) 8 - ns t ch(avg) average clock high pulse width 0.47 0.53 t ck t cl(avg) average clock low pulse width 0.47 0.53 t ck t dqsq dqs, dqs# to dq skew, per group, per access - 100 ps t qh dq output hold time from dqs, dqs# 0.38 - t ck t lz(dq) dq low - impedance time from ck, ck# - 450 225 ps t hz(dq) dq high impedance time fr om ck, ck# - 225 ps t ds(base) data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels ac150 10 - ps t dh(base) data hold time from dqs, dqs# referenced to vih(dc) / vil(dc) levels dc100 45 - ps t dipw dq and dm input pulse width for each inpu t 360 - ps t rpre dqs,dqs# differential read preamble 0.9 - t ck t rpst dqs, dqs# differential read postamble 0.3 - t ck t qsh dqs, dqs# differential output high time 0.4 - t ck t qsl dqs, dqs# differential output low time 0.4 - t ck t wpre dqs, dqs# differen tial write preamble 0.9 - t ck t wpst dqs, dqs# differential write postamble 0.3 - t ck t dqsck dqs, dqs# rising edge output access time from rising ck, ck# - 225 225 ps t lz(dqs) dqs and dqs# low - impedance time (referenced from rl - 1) - 450 225 ps t hz(dqs) dqs and dqs# high - impedance time (referenced from rl + bl/2) - 225 ps t dqsl dqs, dqs# differential input low pulse width 0.45 0.55 t ck t dqsh dqs, dqs# differential input high pulse width 0.45 0.55 t ck t dqss dqs, dqs# rising edge to ck, ck# rising edge - 0.27 0.27 t ck t dss dqs, dqs# falling edge setup time to ck, ck# rising edge 0.18 - t ck t dsh dqs, dqs# falling edge hold time from ck, ck# rising edge 0.18 - t ck t dllk dll locking time 512 - t ck t rtp internal read command to precharge command delay max (4nck, 7.5ns) - t wtr delay from start of internal write transaction to internal read command max (4nck, 7.5ns) - t wr write recovery time 15 - ns t mrd mode register set command cycle time 4 - t ck t mod mode register set command update delay m ax (12nck, 15ns) - confidential - 26/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
t ccd cas# to cas# command delay 4 - t ck t dal(min) auto precharge write recovery + prechargetime wr + t rp t ck t mprr multi - purpose register recovery time 1 - t ck t rrd active to active command period max (4nck, 6 ns) - t faw four activate windo w 30 - ns t is(base) command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels ac175 45 - ps ac150 170 - ps t ih(base) command and address hold time from ck, ck# referenced to vih(dc) / vil(dc) levels dc100 120 - ps t ipw control and address input pulse width for each input 560 - ps t zqinit power - up and reset calibration time 512 - t ck t zqoper normal operation full calibration time 256 - t ck t zqcs normal operation short calibration time 64 - t ck t xpr exit reset from cke high to a valid command m ax (5nck, t rfc +10ns) - t xs exit self refresh to commands not requiring a locked dll m ax (5nck, t rfc +10ns) - t xsdll exit self refresh to commands requiring a locked dll tdllk (min) - t ck t ckesr minimum cke low width for self refresh entry to exit timing tcke (min) + 1 nck - t cksre valid clock requirement after self refresh entry (sre) or power - down entry (pde) m ax (5 nck, 10ns) - t cksrx valid clock requirement before self refresh exit (srx) or power - down exit (pdx) or reset exit m ax (5 nck, 10ns) - t xp exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll m ax (3 nck, 6ns) - t xpdll exit precharge power down with dll frozen to commands requiring a lock eddll m ax (10 nck, 24ns) - t cke cke minimum pulse width m ax (3 nck, 5ns) - t cpded command pass disable delay 2 - t ck t pd power down entry to exit timing tcke(min) 9 * t refi t actpden timing of act command to power down entry 1 - t ck t prpden timing o f pre or prea command to power down entry 1 - t ck t rdpden timing of rd/rda command to power down entry rl + 4 + 1 - t ck t wrpden timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) wl + 4 + (t wr /t ck ) - t ck t wrapden timing of wra command to power down entry (bl8otf, bl8mrs,bc4otf) wl + 4 + wr + 1 - t ck t wrpden timing of wr command to power down entry (bc4mrs) wl + 2 + (t wr /t ck ) - t ck t wrapden timing of wra command to power down entry (bc4mrs) wl + 2 + wr + 1 - t ck t refpden timing of ref co mmand to power down entry 1 - t ck t mrspden timing of mrs command to power down entry tmod (min) - odtlon odt turn on latency wl - 2 = cwl + al - 2 t ck odtloff odt turn off latency wl - 2 = cwl + al - 2 odth4 odt high time without write command or wit h write command and bc4 4 - t ck odth8 odt high time with write command and bl8 6 - t ck t aonpd asynchronous rtt turn - on delay (power - down with dll frozen) 2 8.5 ns confidential - 27/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
t aofpd asynchronous rtt turn - off delay (power - down with dll frozen) 2 8.5 ns t aon rtt turn - on - 225 225 ps t aof rtt_nom and rtt_wr turn - off time from odtloff reference 0.3 0.7 t ck t adc rtt dynamic change skew 0.3 0.7 t ck t wlmrd first dqs/dqs# rising edge after write leveling mode is programmed 40 - t ck t wldqsen dqs/dqs# delay after write leveling mode is programmed 25 - t ck t wls write leveling setup time from rising ck, ck# crossing to rising dqs, dqs# crossing 165 - ps t wlh write leveling hold time from rising dqs, dqs# crossing to rising ck, ck# crossing 165 - ps t wlo write leveling output delay 0 7.5 ns t wloe write leveling output error 0 2 ns t rfc ref command to act or ref command time 260 - ns t refi average periodic refresh interval -4 0c to 85c - 7.8 ? 85c to 105c - 3.9 ? confidential - 28/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
- multi-purpose register (mpr) the multi purpose register (mpr) function is used to read out a predefined system timing calibration bit sequence. figure 8. mpr block diagram memory core (all banks precharged) mrs 3 a2 dq, dm, dqs, dqs# multipurpose register pre-defined data for reads to enable the mpr, a mode register set (mrs) command must be issued to mr3 register with bit a2 = 1 . prior to issuing the mrs command, all banks must be in the idle state (all banks precharged and trp met). once the mpr is enabled, any subsequent rd or rd a commands will be redirected to the multi purpose register. the resulting operation, when a rd or rda command is issued, is defined by mr3 bits a[1:0] when the mpr is enabled as shown in table 20 . when the mpr is enabled, only rd or rda commands are allow ed until a subsequent mrs command is issued with the mpr disabled (mr3 bit a2 = 0). note that in mpr mode rda has the same functionality as a read command which means the auto precharge part of rda is ignored. power - down mode, self - refresh and any other no n- rd/rda command is not allowed during mpr enable mode. the reset function is supported during mpr enable mode. table 19. mpr mr3 register definition mr3 a[2] mr3 a[1:0] function mpr mpr - loc 0b d on t care (0b or 1b) normal operation, no mpr transactio n. all subsequent reads will come from dram array. all subsequent write will go to dram array. 1b see the table 20 enable mpr mode, subsequent rd/rda commands defined by mr3 a[1:0]. confidential - 29/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
- mpr functional description one bit wide logical interfac e via all dq pins during read operation. register read on x 8: dql[0] drive information from mpr. dql[7:1] either drive the same information as dql [0], or they drive 0b. addressing during for multi purpose register reads for all mpr agents: ba [2 :0]: dont care a[1:0]: a[1:0] must be equal to 00b. data read burst order in nibble is fixed a[2]: for bl=8, a[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *) for burst chop 4 cases, the burst order is switched on nibble base a [2]=0b, burst order: 0,1,2,3 *) a[2]=1b, burst order: 4,5,6,7 *) a[9:3]: dont care a10/ap: dont care a12/bc: selects burst chop mode on - the - fly, if enabled within mr0. a11 , a13, ... (if available): dont care regular interface functionality du ring register reads: support two burst ordering which are switched with a2 and a[1:0]=00b. support of read burst chop (mrs and on - the - fly via a12/bc) all other address bits (remaining column address bits including a10, all bank address bits) will be ignored by the ddr3 sdram. regular read latencies and ac timings apply. dll must be locked prior to mpr reads. note: *) burst order bit 0 is assigned to lsb and burst order bit 7 is assigned to msb of the selected mpr agent. table 20. mpr mr3 register definition mr3 a[2] mr3 a[1:0] function burst length read address a[2:0] burst order and data pattern 1b 00b read predefined pattern for system calibration bl8 000b burst order 0, 1, 2, 3, 4, 5, 6, 7 pre - defined data pattern [0, 1, 0, 1, 0, 1, 0, 1] bc4 000b burst order 0, 1, 2, 3 pre - defined data pattern [0, 1, 0, 1] bc4 100b burst order 4, 5, 6, 7 pre - defined data pattern [0, 1, 0, 1] 1b 01b rfu bl8 000b burst order 0, 1, 2, 3, 4, 5, 6, 7 bc4 000b burst order 0, 1, 2, 3 bc4 100b bur st order 4, 5, 6, 7 1b 10b rfu bl8 000b burst order 0, 1, 2, 3, 4, 5, 6, 7 bc4 000b burst order 0, 1, 2, 3 bc4 100b burst order 4, 5, 6, 7 1b 11b rfu bl8 000b burst order 0, 1, 2, 3, 4, 5, 6, 7 bc4 000b burst order 0, 1, 2, 3 bc4 100b bur st order 4, 5, 6, 7 l no operation (nop) command the no operation (nop) command is used to i nstruct the selected ddr3 sdram to perform a nop ( cs# low and ras# , cas# and we# high). this prevents unwanted commands from being registered during idle or wait s tates. operations already in progress are not affected. l deselect command the deselect function ( cs# high) prevents new commands from being executed by the ddr3 sdram. the ddr3 sdram is effectively deselected. operations already in progress are not affecte d. confidential - 30/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l dll - off mode ddr3 dll - off mode is entered by setting mr1 bit a0 to 1 ; this will disable the dll for subsequent operations until a0 bit set back to 0. the mr1 a0 bit for dll control can be switched either during initialization or later. the dll - off mode operations listed below are an optional feature for ddr3 . the maximum clock frequency for dll - off mode is specified by the parameter tckdll_off. there is no minimum frequency limit besides the need to satisfy the refresh interval, trefi. due to la tency counter and timing restrictions, only one value of cas latency (cl) in mr0 and cas write latency (cwl) in mr2 are supported. the dll - off mode is only required to support setting of both cl=6 and cwl=6. dll - off mode will affect the read data clock to data strobe relationship (tdqsck) but not the data strobe to data relationship (tdqsq, tqh). special attention is needed to line up read data to controller time domain. comparing with dll - on mode, where tdqsck starts from the rising clock edge (al+cl) cyc les after the read command, the dll - off mode tdqsck starts (al+cl - 1) cycles after the read command. another difference is that tdqsck may not be small compared to tck (it might even be larger than tck) and the difference between tdqsckmin and tdqsckmax is significantly larger than in dll - on mode. the timing relations on dll - off mode read operation have shown at the following timing diagram (cl=6, bl=8) figure 9. dll -off mode read timing operation ck# t1 t2 t3 t4 t5 t6 t7 t8 t9 t0 address ck t10 command dqs# dqs don't care nop read nop nop nop nop nop nop nop nop nop bank, col b rl (dll_on) = al + cl = 6 (cl = 6, al = 0) cl = 6 din b din b+1 din b+2 din b+3 din b+4 din b+5 din b+6 din b+7 dq din b din b+1 din b+2 din b+3 din b+4 din b+5 din b+6 din b+7 dqs# dqs dq din b din b+1 din b+2 din b+3 din b+4 din b+5 din b+6 din b+7 dqs# dqs dq (dll_on) (dll_on) (dll_off) (dll_off) (dll_off) (dll_off) rl (dll_off) = al + (cl-1) = 5 t dqsck(dll_off)_min t dqsck(dll_off)_max note 1. the tdqsck is used here for dqs, dqs# and dq to have a simplified diagram; the dll_off shift will affect both timings in the same way and the skew between all dq and dqs, dqs# signals will still be tdqsq. transitioning data confidential - 31/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l dll on/off switching procedure ddr3 dll - off mode is entered by setting mr1 bit a0 to 1; this will disable the dll for subsequent operation until a0 bit set back to 0. l dll ?n?to dll ?ff?procedure to switch from dll on to dll off requires the frequency to be chang ed during self - refresh outlined in the following procedure: 1 . starting from idle state (all banks pre - charge d , all timing fulfilled, and drams on - die termination resistors, rtt, must be in high impedance state before mrs to mr1 to disable the dll). 2 . set mr1 bit a0 to 1 to disable the dll. 3 . wai t tm od. 4 . enter se lf refresh mode; wait until (tcksre) satisfied. 5 . change frequency, in guidance with input clock frequency change section. 6 . wait until a stable clock is available for at least (tcksrx) at dra m in p uts. 7 . starting with the self refresh exit command, cke must continuously be registered high until all tmod timings from any mrs command are satisfied. in addition, if any odt features were enabled in the m ode registers when self refres h mode was entered, the odt signal must continuously be registered low until all tmod timings from any mrs command are satisfied. if both odt features were disabled in the mode registers when self refresh mode was entered, odt signal can be registered low or high. 8 . wait txs, and then set mode registers with appropriate values (especially an update of cl, cwl, and wr may be necessary. a zqcl command may also be issued after txs). 9 . wait for tmod, and then dram is ready for next command. figure 10. dll switch sequence from dll-on to dll-off t1 ta0 ta1 tb0 tc0 td0 td1 te0 te1 t0 tf0 t mod notes 1 don't care time break nop mrs sre nop srx nop mrs nop valid valid t cksre notes 2 notes 3 notes 6 notes 7 notes 8 notes 8 notes 4 t cksrx notes 5 t xs t mod t ckesr valid notes 8 notes: 1. starting with idle state, rtt in hi-z state 2. disable dll by setting mr1 bit a0 to 1 3. enter sr 4. change frequency 5. clock must be stable tcksrx 6. exit sr 7. update mode registers with dll off parameters setting 8. any valid command odt: static low in case rtt_nom and rtt_wr is enabled, otherwise static low or high ck# ck command cke odt confidential - 32/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l dll ?ff?to dll ?n?procedure to switch from dll off to dll on (with requires frequency change) during self - refresh: 1 . starting from idle state (all banks pre - charged, all timings fu lfilled and dra ms on - die termination resistors (rtt) must be in high impedance state before self - refresh mode is entered). 2 . enter self refresh mode, wait until tcksre satisfied. 3 . change frequency, in guidance with input clock frequency change section . 4 . wait until a stable clock is available for at least (tcksrx) at dram inputs. 5 . starting with the self refresh exit command, cke must continuously be registered high until tdllk timing from subse q uent dll reset command is satisfied. in addition, if an y odt features were enabled in the mode registers when self refresh mode was entered , the odt signal must continuously be registered low until tdllk timings from subsequent dll reset command is satisfied. if both odt features are disabled in the mode regis ters when self refresh mode was entered, odt signal can be registered low or high. 6 . wait txs, then set mr1 bit a0 to 0 to enable the dll. 7 . wait tmrd, then set mr0 bit a8 to 1 to start dll reset. 8 . wait tmrd, then set mode registers with appropriat e values ( especially an update of cl, cwl, and wr may be necessary. after tmod satisfied from any proceeding mrs command, a zqcl command may also be issued during or af ter t d llk). 9 . wait for tmod, then dram is ready for next command (remember to wait tdll k after dll reset before applying command requiring a locked dll!). in addition, wait also for tzqoper in case a zqcl command wa s issued. figure 11. dll switch sequence from dll-off to dll on ck# ta0 ta1 tb0 tc0 tc1 td0 te0 tf1 tg0 t0 ck th0 command cke odt notes 1 don't care time break sre nop nop srx mrs mrs mrs valid valid t cksre notes 2 notes 5 notes 7 notes 3 t cksrx notes 4 t xs t mrd t ckesr notes: 1. starting with idle state 2. enter sr 3. change frequency 4. clock must be stable tcksrx 5. exit sr 6. set dll on by mr1 a0 = 0 7. start dll reset by mr0 a8=1 8. update mode registers 9. any valid command odt: static low in case rtt_nom and rtt_wr is enabled, otherwise static low or high notes 6 notes 8 t dllk odtloff + 1 * tck t mrd notes 9 confidential - 33/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l jitter notes note 1. unit tck(avg) represents the actual tck(avg) of the input clock under operation. unit nck represents one clock cycle of the input clock, counting the actual clock edges.ex) tmrd = 4 [nck] means; if one mode register set command is registered at tm, ano ther mode register set command may be registered at tm+4, even if (tm+4 - tm) is 4 x tck(avg) + terr(4per),min. n ote 2. these parameters are measured from a command/address signal (cke, cs#, ras#, cas#, we#, odt, ba0, a0, a1, etc.) transition edge to its r espective clock signal (ck/ck#) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. that is, th ese parameters should be met whether clock jitter is present or not. n ote 3. these parameters are measured from a data strobe signal (dqs, dqs#) crossing to its respective clock signal (ck, ck#) crossing. the spec values are not affected by the amount of c lock jitter applied (i.e. tjit(per), tjit(cc), etc.), as these are relative to the clock signal crossing. that is, these parameters should be met whether clock jitter is present or not. n ote 4. these parameters are measured from a data signal (dm, dq0, dq1 , etc.) transition edge to its respective data strobe signal (dqs, dqs#) crossing. n ote 5. for these parameters, the ddr3 sdram device supports tnparam [nck] = ru{ tparam [ns] / tck(avg) [ns] }, which is in clock cycles, assuming all input clock jitter spe cifications are satisfied. n ote 6. when the device is operated with input clock jitter, this parameter needs to be derated by the actual terr(mper),act of the input clock, where 2 <= m <= 12. (output deratings are relative to the sdram input clock.) n ote 7. when the device is operated with input clock jitter, this parameter needs to be derated by the actual tjit(per),act of the input clock. (output deratings are relative to the sdram input clock.) table 21. input clock jitter spec parameter parameter sy mbol - 12 unit min . max . clock period jitter t jit (per) - 70 70 ps clock period jitter during dll locking period t jit (per,lck) - 60 60 ps cycle to cycle clock period jitter t jit (cc) 140 ps cycle to cycle clock period jitter during dll locking perio d t jit (cc,lck) 120 ps cumulative error across 2 cycles t err (2per) - 103 103 ps cumulative error across 3 cycles t err (3per) - 122 122 ps cumulative error across 4 cycles t err (4per) - 136 136 ps cumulative error across 5 cycles t err (5per) - 147 147 ps cumulative error across 6 cycles t err (6 per) - 155 155 ps cumulative error across 7 cycles t err (7 per) - 163 163 ps cumulative error across 8 cycles t err (8 per) - 169 169 ps cumulative error across 9 cycles t err (9 per) - 175 175 ps cumulative error across 10 cycles t err ( 10per) - 180 180 ps cumulative error across 11 cycles t err ( 11per) - 184 184 ps cumulative error across 12 cycles t err ( 12per) - 188 188 ps cumulative error across n cycles, n=1 3 ...50, inclusive t err (n per) t err (n per) min = (1+0.68ln(n)) * t jit (per) min t err (n per) max = (1+0.68ln(n)) * t jit (per) max ps confidential - 34/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l input clock frequency change once the ddr3 sdram is initialized, the ddr3 sdram requires the clock to be stable during almost all states of normal operation. this means once the clock frequency has been set and is to be in the stable state, the clock period is not allowed to deviate except for what is allowed for by the clock jitter and ssc (spread spectrum clocking) specification. the input clock frequency can be changed from one sta ble clock rate to another stable clock rate under two conditions: (1) self - refresh mode and (2) precharge power - down mode. outside of these two modes, it is illegal to change the clock frequency. for the first condition, once the ddr3 sdram has been succes sfully placed in to self - refresh mode and tcksre has been satisfied, the state of the clock becomes a dont care. once a dont care, changing the clock frequency is permissible, provided the new clock frequency is stable prior to tcksrx. when entering and exiting self - refresh mode of the sole purpose of changing the clock frequency , the self - refresh entry and exit specifications must still be met . the ddr3 sdram input clock frequency is allowed to change only within the minimum and maximum operating frequen cy specified for the particular speed grade. the second condition is when the ddr3 sdram is in precharge power - down mode (either fast exit mode or slow exit mode). if the rtt_nom feature was enabled in the mode register prior to entering precharge power d own mode, the odt signal must continuously be registered low ensuring rtt is in an off state. if the rtt_nom feature was disabled in the mode register prior to entering precharge power down mode, rtt will remain in the off state. the odt signal can be regi stered either low or high in this case. a minimum of tcksre must occur after cke goes low before the clock frequency may change. the ddr3 sdram input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade. during the input clock frequency change, odt and cke must be held at stable low levels. once the input clock frequency is changed, stable new clocks must be provided to the dram tcksrx before precharge power down may be exited; after precharge power down is exited and txp has expired, the dll must be reset via mrs. depending on the new clock frequency additional mrs commands may need to be issued to appropriately set the wr, cl, and cwl with cke continuously registered high. dur ing dll re - lock period, odt must remain low and cke must remain high. after the dll lock time, the dram is ready to operate with new clock frequency. figure 1 2. change frequency during precharge power- down ck# t1 t2 ta0 tb0 tc0 tc1 td0 td1 te0 t0 address ck te1 command odt nop nop nop nop nop mrs nop valid dll reset high-z high-z dqs# dqs dq dm notes 1. applicable for both slow exit and fast exit precharge power-down. 2. taofpd and taof must be statisfied and outputs high-z prior to t1;refer to odt timing section for exact requirements 3. if the rtt_nom feature was enabled in the mode register prior to entering precharge power down mode, the odt signal must continuously be registered low ensuring rtt is in an off state, as shown in figure 9. if the rtt_nom feature was disabled in the mode register prior to entering precharge power down mode, rtt will remain in the off state. the odt signal can be registered either low or high in this case . t ch t cl t ck t cksre t chb t clb t ckb t chb t clb t ckb t chb t clb t ckb t cksrx t cke cke t ih t is valid t xp enter precharge power-down mode t cpded previous clock frequency new clock frequency t aofpd / t aof frequency change exit precharge power-down mode t dllk don't care indicates a break in time scale t ih t is t ih t is confidential - 35/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l write leveling for better signal integrity, ddr3 memory adopted fly by topology for the commands, addresses, control signals, and clocks. the fly by topology has benefits from reducing number of stubs and their length but in other aspect, causes flight time skew between clo ck and strobe at every dram on dimm. it makes it difficult for the controller to maintain tdqss, tdss, and tdsh specification. therefore, the controller should support write leveling in ddr3 sdram to compensate the skew. the memory controller can use the ?rite leveling? feature and feedback from the ddr3 sdram to adjust the dqs dqs# to ck ck# relationship. the memory controller involved in the leveling must have adjustable delay setting on dqs dqs# to align the rising edge of dqs dqs# with that o f the clock at the dram pin. dram asynchronously feeds back ck ck# , sampled with the rising edge of dqs dqs# , through the dq bus. the controller repeatedly delays dqs dqs# until a transition from 0 to 1 is detected. the dqs dqs# delay established though this exercise would ensure tdqss specification. besides tdqss, tdss, and tdsh specification also needs to be fulfilled. one way to achieve this is to combine the actual tdqss in the application with an appropriate duty cycle and jitter on the dqs - dq s# signals. depending on the actual tdqss in the application, the actual values for tdqsl and tdqsh may have to be better than the absolute limits provided in ?c timing parameters?section in order to satisfy tdss and tdsh specification. dqs/dqs# driven by the controller during leveling mode must be determined by the dram based on ranks populated. similarly, the dq bus driven by the dram must also be terminated at the controller. one or more data bits should carry the leveling feedback to the controller across the dram configurations x8. therefore, a separate feedback mechanism should be available for each byte lane. figure 1 3. write leveling concept ck# t1 t2 t3 t4 t5 t6 t7 t0 ck diff_dqs dq source destination t0 t1 t2 t3 t4 t5 t6 tn ck# ck diff_dqs 0 0 dq diff_dqs 1 1 push dqs to capture 0-1 transition 0 or 1 0 or 1 0 1 confidential - 36/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l dram setting for write leveling and dram termination function in that mode dram enters into write leveling mode if a7 in mr1 set high and after finishing leveling, dram exits from write leveling mode if a7 in mr1 set low. note that in write leveling mode, only dqs/ dqs# terminations are activated and deactivated via odt pin not like normal operation. table 22. dram termination function in the leveling mode odt pi n at dram dqs, dqs# termination dqs termination de - asserted off off asserted on off note 1: in write leveling mode with its output buffer disabled (mr1[ bit7]=1 with mr1[bit12]=1) all rtt_nom se ttings are allowed; in write leveling mode with its output buffer enabled (mr1[bit7]=1 with mr1[bit12]=0) only rtt_nom settings of rzq/2, rzq/4, and rzq/6 are allowed. l procedure description memory controller init iates leveling mode of all drams by setting bit 7 of mr1 to 1. with entering write leveling mode, the dq pins are in undefined driving mode. during write leveling mode, only nop or deselect commands are allowed. as well as an mrs command to exit write leve ling mode. since the controller levels one rank at a time, the output of other rank must be disabled by setting mr1 bit a12 to 1. controller may assert odt after tmod, time at which dram is ready to accept the odt signal. controller may drive dqs low and d qs# high after a delay of twldqsen, at which time dram has applied on - die termination on these signals. after tdqsl and twlmrd controller provides a single dqs, dqs# edge which is used by the dram to sample ck ck# driven from controller. twlmrd(max) timing is controller dependent. dram samples ck ck# status with rising edge of dqs and provides feedback on all the dq bits asynchronously after twlo timing. there is a dq output uncertainty of twloe defined to allow mismatch on dq bits; there are no read s trobes (dqs/dqs) needed for these dqs. controller samples incoming dq and decides to increment or decrement dqs dqs# delay setting and launches the next dqs/ dqs# pulse after some time, which is controller dependent. once a 0 to 1 transition is detected, the controller locks dqs dqs# delay setting and write leveling is achieved for the device. figure 14 . timing details of write leveling sequence ( dqs dqs# is capturing ck ck# low at t1 and ck ck# high at t2 ) t wlmrd don't care time break nop mrs nop nop nop nop nop nop nop nop nop t wls t wlh t1 t wls t wlh t2 nop notes 1 notes 2 t wldqsen t dqsl notes 6 t dqsh notes 6 t dqsl notes 6 t dqsh notes 6 ck# ck command odt diff_dqs prime dq notes 5 notes 4 one prime dq: notes 3 late prime dqs early prime dqs all dqs are prime: notes 3 notes 3 late remaining dqs early remaining dqs t wlo t wlo t wlo t wloe t wlo t wloe t wlo t mod t wlo t wlmrd t wlo t wlo t wloe undefined driving mode notes 1. mrs: load mr1 to enter write leveling mode. 2. nop: nop or deselect. 3. dram has the option to drive leveling feedback on a prime dq or all dqs. if feedback is driven only on one dq, the remaining dqs must be driven low, as shown in above figure, and maintained at this state through out the leveling procedure. 4. diff_dqs is the differential data strobe (dqs, dqs#). timing reference points are the zero crossings. dqs is shown with solid line, dqs# is shown with dotted line. 5. ck, ck# : ck is shown with solid dark line, where as ck# is drawn with dotted line. 6. dqs, dqs# needs to fulfill minimum pulse width requirements tdqsh(min) and tdqsl(min) as defined for regular writes; the max pulse width is system dependent. confidential - 37/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l write leveling mode exit the following sequence describes how write leveling mode should be exited: 1. after the last rising strobe edge (see ~t0), stop driving the strobe signals (see ~tc0). note: from now on, dq pins are in undefined driving mode, and will remain undefined, until tmod after the respective mr command (te1). 2. drive odt pin low (tis must be satisfied) and keep it low (see tb0). 3. after the rtt is switched off, disable write level mode via mrs command (see tc2). 4. after tmod is satisfied (te1), a ny valid command may be registered. (mr commands may be issued after tmrd (td1). figure 15 . timing de tails of write leveling exit don't care time break nop nop nop nop nop nop nop mrs nop valid nop valid t wlo t aofmin undefined driving mode t1 t2 ta0 tb0 tc0 tc1 tc2 t0 td0 td1 te0 te1 notes: 1. the dq result = 1 between ta0 and tc0 is a result of the dqs, dqs# signals capturing ck high just after the t0 state. mr1 valid valid t mrd rtt_nom result = 1 transitioning t aofmax t is odtloff t mod ck# ck command address odt rtt_dqs_dqs# dq dqs_dqs# rtt_dq notes 1 l extended temperature usage users should refer to the dram supplier data sheet and/or the dim m spd to determine if ddr3 sdram devices support the following options or requirements referred to in this material: 1. auto self - refresh supported 2. extended temperature range supported 3. double refresh required for operation in the extended temperature range (applies only for devices supporting the extended temperature range) l auto self-refresh mode - asr mode ddr3 sdram provides an auto - refresh mode (asr) for application ease. asr mode is enabled by setting mr2 bit a6=1 and mr2 bit a7=0. the dram will manage self - refresh entry in either the normal or extended temperature ranges . in this mode, the dram will also manage self - refresh power consumption when the dram operating temperature changes, lower at low temperatures and higher at high temperatures. if the asr option is not supported by dram, mr2 bit a6 must set to 0. if the asr option is not enabled (mr2 bit a6=0), the srt bit (mr2 bit a7) must be manually programmed with the operating temperature range required during self - refresh operation. support o f the asr option does not automatically imply support of the extended temperature range. confidential - 38/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l self-refresh temperature range - srt srt applies to devices supporting extended temperature range only. if asr=0, the self - refresh temperature (srt) range bit mu st be programmed to guarantee proper self - refresh operation. if srt=0, then the dram will set an appropriate refresh rate for self - refresh operation in the normal temperature range. if srt=1, then the dram will set an appropriate, potentially different, re fresh rate to allow self - refresh operation in either the normal or extended temperature ranges. the value of the srt bit can effect self - refresh power consumption, please refer to idd table for details. table 23. self-refresh mode summary mr2 a[6] mr2 a[7 ] self - refresh operation allowed operating temperature range for self - refresh mode 0 0 self - refresh rate appropriate for the normal temperature range normal (0 ~ 85c) 0 1 self - refresh appropriate for either the normal or extended temperature ranges.the dram must support extended temperature range. the value of the srt bit can effect self - refresh power consumption, please refer to the idd table for details. normal and extended ( 0 ~ 95c) 1 0 asr enabled (for devices supporting asr and normal temperature ra nge).self - refresh power consumption is temperature dependent. normal (0 ~ 85c) 1 0 asr enabled (for devices supporting asr and extended temperature range).self - refresh power consumption is temperature dependent. normal and extended (0 ~ 95c) 1 1 illegal l active command the active command is used to open (or activate) a row in a particular bank for subsequent access. the value on the ba0 - ba2 inputs selects the bank, and the addresses provided on inputs a0 - a1 5 selects the row. these rows remain active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. l precharge command the precharge command is used to deactivate the open row in a particular bank or t he open row in all banks. the bank(s) will be available for a subsequent row activation a specified time (trp) after the precharge command is issued, except in the case of concurrent auto precharge, where a read or write command to a different bank is allo wed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command is allowed if there is no open row in that bank (idle bank) or if the previously open row is already in the process of precharging. however, the precharge period will be determined by the last precharge command issued to the bank. confidential - 39/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
read operation l read burst operation durin g a read or write command ddr3 will support bc4 and bl8 on the fly using address a12 during the read or write (auto precharge can be enabled or disabled). a12=0, bc4 (bc4 = burst chop, tccd=4) a12=1, bl8 a1 2 will be used only for burst length control, not a column address. figure 16 . read burst operation rl=5 (al=0, cl=5, bl=8) don't care nop read nop nop nop nop nop nop nop nop nop notes: 1. bl8, rl = 5, al = 0, cl = 5. 2. dout n = data-out from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0 = 00] or mr0[a1:0 = 01] and a12 = 1 during read command at t0. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 bank, col n transitioning data t rpre t rpst dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 rl = al + cl cl = 5 ck# ck dqs, dqs# dq notes 3 notes 2 address notes 4 command figure 17 . read burst operation rl=9 (al=4, cl=5, bl=8) don't care nop read nop nop nop nop nop nop nop nop nop notes: 1. bl8, rl = 9, al = (cl-1), cl = 5. 2. dout n = data-out from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0 = 00] or mr0[a1:0 = 01] and a12 = 1 during read command at t0. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 bank, col n transitioning data t rpre dout n dout n+1 dout n+2 rl = al + cl al = 4 cl = 5 ck# ck dqs, dqs# dq notes 3 notes 2 address notes 4 command confidential - 40/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l read timing definitions read timing is shown in the following figure and is applied when the dll is enabled and locked. rising data strobe edge parameters: tdqsck min/max describes the allowed range for a rising data strobe edge relative to ck, ck# . tdqsck is t he actual position of a rising strobe edge relative to ck, ck# . tqsh describes the dqs, dqs# differential output high time. tdqsq describes the latest valid transition of the associated dq pins. tqh describes the earliest invalid transition of the associat ed dq pins. falling data strobe edge parameters: tqsl describes the dqs, dqs# differential output low time. tdqsq describes the latest valid transition of the associated dq pins. tqh describes the earliest invalid transition of the associated dq pi ns. tdq sq; both rising/falling edges of dqs, no tac defined. figure 18 . read timing definition t dqsck t dqsck,min ck# ck t dqsck,max t dqsck,max rising strobe region t dqsck,min dqs# dqs t dqsck t qsh t qsl rising strobe region associated dq pins t qh t qh t dqsq t dqsq confidential - 41/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l read timing; clock to data strobe relationship clock to data strobe relationship is shown in the following figure and i s applied when the dll is enabled and locked. rising data strobe edge parameters: tdqsck min/max describes the allowed range for a rising data strobe edge relative to ck and ck# . tdqsck is the actual position of a rising strobe edge relative to ck and ck# . tqsh describes the data strobe high pulse width. falling data strobe edge parameters: tqsl describes the data strobe low pulse width. figure 19. clock to data strobe relationship notes: 1. within a burst, rising strobe edge is not necessarily fixed to be always at tdqsck(min) or tdqsck(max). instead, rising strobe edge can vary between tdqsck(min) and tdqsck(max). 2. notwithstanding note 1, a rising strobe edge with tdqsck(max) at t(n) can not be immediately followed by a rising strobe edge with tdqsck(min) at t(n+1). this is because other timing relationships (tqsh, tqsl) exist: if tdqsck(n+1) < 0: tdqsck(n) < 1 . 0 tck - (tqshmin + tqslmin) - | tdqsck(n+1) | 3. the dqs, dqs# differential output high time is defined by tqsh and the dqs, dqs# differential output low time is defined by tqsl. 4. likewise, tlz(dqs)min and thz(dqs)min are not tied to tdqsckmin (early strobe case) and tlz(dqs)max and thz(dqs)max are not tied to tdqsckmax (late strobe case). 5. the minimum pulse width of read preamble is defined by trpre(min). 6. the maximum read postamble is bound by tdqsck(min) plus tqsh(min) on the left side and thzdsq(max) on the right side. 7. the minimum pulse width of read postamble is defined by trpst( min). 8. the maximum read preamble is bound by tlzdqs(min) on the left side and tdqsck(max) on the right side. clk# clk t lz(dqs) min dqs, dqs# late strobe dqs, dqs# early strobe t rpre t lz(dqs) max t dqsck (min) t qsh t qsl t dqsck (min) t qsh t qsl t qsh t qsl t dqsck (min) t dqsck (min) t rpst t hz(dqs) (min) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 t dqsck (max) t rpre t qsh t qsl t dqsck (max) t qsh t qsl t qsh t qsl t dqsck (max) t dqsck (max) t rpst t hz(dqs) (max) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 rl measured to this point confidential - 42/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l read timing; data strobe to data relationship the data strobe to data relationship is shown in the following figure and is applied when the dll and enabled and locked. rising data strobe edge parameters: - tdqsq describes the latest valid transition of the associated dq pins. - tqh d escribes the earliest invalid transition of the associated dq pins. falling data strobe edge parameters: - tdqsq describes the latest valid transition of the associated dq pins. - tqh describes the earliest invalid transition of the associated dq pins. - t dqsq; both rising/falling edges of dqs, no tac defined tdqsq; both rising/falling edges of dqs, no tac defined . figure 2 0. data strobe to data relationship t1 t2 t3 t4 t5 t6 t7 t8 t9 t0 t10 rl = al +cl nop read nop nop nop nop nop nop nop nop nop bank, col n t dqsq (max) dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 ck# address ck command dqs,dqs# dq (last data valid) all dqs collectively dq (first data no longer valid) t rpre t qh t qh t dqsq (max) t rpst notes 3 notes 4 notes 2 notes 2 notes: 1. bl = 8, rl = 5 (al = 0, cl = 5) 2. dout n = data-out from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0 = 00] or mr0[a1:0 = 01] and a12 = 1 during read command at t0. 5. output timings are referenced to vddq/2, and dll on for locking. 6. tdqsq defines the skew between dqs,dqs# to data and does not define dqs,dqs# to clock. 7. early data transitions may not always happen at the same dq. data transitions of a dq can vary (either early or late) within a burst. don't care transitioning data dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 confidential - 43/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
write operation l ddr3 burst operation during a read or write command, ddr3 will support bc4 and bl8 on the fly using address a12 during the read or write (auto precharge can be enabled or disabled). a12=0, bc4 (bc4 = burst chop, tccd=4) a12=1, bl8 a12 is used only for burst length control, not as a column addres s. l write timing violations generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure the dram works properly. however, it is desirable for certain minor violations that the dram is guaranteed not to ha ng up and errors be limited to that particular operation. for the following, it will be assumed that there are no timing violations with regard to the write command itself (including odt, etc.) and that it does satisfy all timing requirements not mentione d below. l data setup and hold violations should the strobe timing requirements (tds, tdh) be violated, for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with the offending write com mand. subsequent reads from that location might result in unpredictable read data, however, the dram will work properly otherwise. l strobe to strobe and strobe to clock violations should the strobe timing requirements (tdqsh, tdqsl, twpre, twpst) or the st robe to clock timing requirements (tdss, tdsh, tdqss) be violated, for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with the offending write command. subsequent reads from that loc ation might result in unpredictable read data, however the dram will work properly otherwise. l write timing parameters this drawing is for example only to enumerate the strobe edges that belong to a write burst. no actual timing violations are shown here . for a valid burst all timing parameters for each edge of a burst need to be satisfied (not only for one edge ). l refresh command the refresh command (ref) is used during normal operation of the ddr3 sdrams. this command is not persistent, so it must be i ssued each time a refresh is required. the ddr3 sdram requires refresh cycles at an average periodic interval of trefi. when cs# , ras# , and cas# are held low and we# high at the rising edge of the clock, the chip enters a refresh cycle. all banks of the sdram must be precharged and idle for a minimum of the precharge time trp(min) before the refresh command can be applied. the refresh addressing is generated by the internal refresh controller. this makes the address bits dont care during a refresh comman d. an internal address counter suppliers the address during the refresh cycle. no control of the external address bus is required once this cycle has started. when the refresh cycle has completed, all banks of the sdram will be in the precharged (idle) sta te. a delay between the refresh command and the next valid command, except nop or des, must be greater than or equal to the minimum refresh cycle time trfc(min) . in general, a refresh command needs to be issued to the ddr3 sdram regularly every trefi inte rval. to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of 8 refresh commands can be postponed during operation of the ddr3 sdram, meaning that at no point i n time more than a total of 8 refresh commands are allowed to be postponed. in case that 8 refresh commands are postponed in a row, the resulting maximum interval between the surrounding refresh commands is limited to 9 x trefi. a maximum of 8 additional r efresh commands can be issued in advance (pulled in), with each one reducing the number of regular refresh commands required later by one. note that pulling in more than 8 refresh commands in advance does not further reduce the number of regular refresh commands required later, so that the resulting maximum interval between two surrounding refresh command is limited to 9 x trefi. before entering self - refresh mode, all postponed refresh commands must be executed. confidential - 44/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l self-refresh operation the self - refresh command can be used to retain data in the ddr3 sdram, even if the reset of the system is powered down. when in the self - refresh mode, the ddr 3 sdram retains data without external clocking. the ddr3 sdram device has a built - in timer to accommodate self - ref resh operation. the self - refresh entry (sre) command is defined by having cs # , ras# , cas# , and cke held low with we # high at the rising edge of the clock. before issuing the self - refr eshing - entry command, the ddr3 sdram must be idle with all bank precharg e state with trp satisfied. also, on - die termination must be turned off before issuing self - refresh - entry command, by either registering odt pin low odtl + 0.5tck prior to the self - refresh entry command or using mrs to mr1 command. once the self - refresh entry command is registered, cke must be held low to keep the device in self - refresh mode. during normal operation (dll on), mr1 (a0=0), the dll is automatically disabled upon entering self - refresh and is automatically enabled (including a dll - reset) upon exiting self - refresh. when the ddr3 sdram has entered self - refresh mode, all of the external control signals, except cke and reset# , are ?ont care? for proper self - refresh operation, all power supply and reference pins (vdd, vddq, vss, vssq, vrefca, and vrefdq) must be at valid levels. the dram initiates a minimum of one refresh command internally within tcke period once it enters self - refresh mode. the clock is internally disabled during self - refresh operation to save power. the minimum time that the d dr3 sdram must remain in self - refresh mode is tcke. the user may change the external clock frequency or halt the external clock tcksre after self - refresh entry is registered; however, the clock must be restarted and stable tcksrx before the device can exit self - refresh mode. the procedure for exiting self - refresh requires a sequence of events. first, the clock must be stable prior to cke going back high. once a self - refresh exit command (srx, combination of cke going high and either nop or deselect on comm and bus) is registered, a delay of at least txs must be satisfied before a valid command not requiring a locked dll can be issued to the device to allow for any internal refresh in progress. before a command which requires a locked dll can be applied, a de lay of at least txsdll and applicable zqcal function requirements [tbd] must be satisfied. before a command that requires a locked dll can be applied, a delay of at least txsdll must be satisfied. depending on the system environment and the amount of tim e spent in self - refresh, zq calibration command may be required to compensate for the voltage and temperature drift as described in zq calibration c ommands . to issue zq calibration commands, applicable timing requirements must be satisfied. cke must rem ain high for the entire self - refresh exit period txsdll for proper operation except for self - refresh re - entry. upon exit from self - refresh, the ddr3 sdram can be put back into self - refresh mode after waiting at least txs period and issuing one refresh command (refresh period of trfc). nop or deselect commands must be registered on each positive clock edge during the self - refresh exit interval txs. odt must be turned off during txsdll. the use of self - refresh mode instructs the possibility that an internall y times refresh event can be missed when cke is raised for exit from self - refresh mode. upon ex it from self - refresh, the ddr3 sdram requires a minimum of one extra refresh command before it is put back into self - refresh mode. confidential - 45/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
power-down modes l power-down entry and exit power - down is synchronously entered when cke is registered low (along with nop or deselect command). cke is not allowed to go low while mode register set command, mpr operations, zqcal operations, dll locking or read/write operation are in p rogress. cke is allowed to go low while any of other operation such as row activation, precharge or auto precharge and refresh are in progress, but power - down idd spec will not be applied until finishing those operation. the dll should be in a locked state when power - down is entered for fastest power - down exit timing. if the dll is not locked during power - down entry, the dll must be reset after exiting power - down mode for proper read operation and synchronous odt operation. dram design provides all ac and d c timing and voltage specification as well proper dll operation with any cke intensive operations as long as dram controller complies with dram specifications. during power - down, if all banks are closed after any in progress commands are completed, the dev ice will be in precharge power - down mode; if any bank is open after in progress commands are completed, the device will be in active power - down mode. entering power - down deactivates the input and output buffers, excluding ck, ck, odt, cke , and reset# . to protect dram internal delay on cke line to block the input signals, multiple nop or deselect commands are needed during the cke switch off and cycle(s) after, this timing period are defined as tcpded. cke_low will result in deactivation of command and addr ess receivers after tcpded has expired. table 24. power-down entry definitions status of dram mrs bit a12 dll pd exit relevant parameters active (a bank or more open) don't care on fast txp to any valid command. precharged (all banks precharged) 0 off slow txp to any valid command. since it is in precharge state, commands here will be act, ar, mrs/emrs, pr or pra. txpdll to commands who need dll to operate, such as rd, rda or odt control line. precharged (all banks precharged) 1 on fast txp to any vali d command. also the dll is disabled upon entering precharge power - down (slow exit mode), but the dll is kept enabled during precharge power - down (fast exit mode) or active power - down. in power - down mode, cke low, reset# high, and a stable clock signal m ust be mainta ined at the inputs of the dd 3 sdram, and odt should be in a valid state but all other input signals are dont care (if reset# goes low during power - down, the dram will be out of pd mode and into reset state). cke low must be maintain until tcke has been satisfied. power - down duration is limited by 9 times trefi of the device. the power - down state is synchronously exited when cke is registered high (along with a nop or deselect command).cke high must be maintained until tcke has been satisfied . a valid, executable command can be applied with power - down exit latency, txp and/or txpdll after cke goes high. power - down exit latency is defined at ac spec table of this datasheet. confidential - 46/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
on-die termination (odt) on - die termination (odt) is a feature that enables the dram to enable/disable and turn on/off termination resistance for each dq, dqs, dqs#, and dm for the x8 configurations (and tdqs, tdqs# for the x8 configuration, when enabled). odt is designed to improve signal integrity of the memory channel by enabling the dram controller to independently turn on/off the dram s internal termination resistance for any grouping of dram devices. odt is not supported during dll disable mode (simple functional representation shown below). the switch is enabled by the internal odt control logic, which uses the external odt ball and other control information. figure 21. functional representation of odt to other circuitry like rcv,... dq, dqs, dm, tdqs odt vddq / 2 rtt switch the switch is enabled by the internal odt control logic, which uses the external odt pi n and other control information. the value of rtt is determined by the settings of mode register bits. the odt pin will be ignored if the mode register mr1 and mr2 are programmed to disable odt and in self - refresh mode. l odt mode register and odt truth table the odt mode is enabled if either of mr1 {a2, a6, a9} or mr2 {a9, a10} are non -z ero. in this case, the value of rtt is determined by the settings of those bits. application: controller sends wr command together with odt asserted. one possible applicati on: the rank that is being written to provides termination. dram turns on termination if it sees odt asserted (except odt is disabled by mr) dram does not use any write or read command decode information. table 25. termination turth table odt pin dram termination state 0 o ff 1 on, (off, if disabled by mr1 (a2, a6, a9) and mr2 (a9, a10) in gereral) confidential - 47/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l synchronous odt mode synchronous odt mode is selected whenever the dll is turned on and locked. based on th e power - down definition, these modes are: - any bank active with cke high - refresh with cke high - idle mode with cke high - active power down mode (regardless of mr0 bit a12) - precharge power down mode if dll is enabled during precharge power down by mr0 bit a12 the direct odt feature is not sup ported during dll - off mode. the on - die termination resistors must be disabled by continuously registering the odt pin low and/or by programming the rtt_nom bits mr1{a9,a6,a2} to {0,0,0} via a mode register set command during dll - off mode. in synchronous od t mode, rtt will be turned on odtlon clock cycles after odt is sampled high by a rising clock edge and turned off odtloff clock cycles after odt is registered low by a rising clock edge. the odt latency is tied to the write latency (wl) by : odtlon = wl - 2 ; odtloff = wl - 2. l odt latency and posted odt in synchronous odt mode, the additive latency (al) programmed into the mode registe r (mr1) also applies to the odt signal. the dram internal odt signal is delayed for a number of clock cycles defined by the ad ditive latency (al) relative to the external odt signal. odtlon = cwl + al - 2; odtloff = cwl + al - 2. for details, refer to ddr3 sdram latency definitions. table 26. odt latency symbol parameter ddr3 -1 600 unit odtlon odt turn on latency wl 2 = cwl + al -2 tck odtloff odt turn off latency wl 2 = cwl + al -2 tck l timing parameters in synchronous odt mode, the following timing parameters apply: odtlon, odtloff, taon min/max, taof min/max. minimum rtt turn - on time (taon min) is the point in time when the device leaves high impedance and odt resistance begins to turn on. maximum rtt turn - on time (taon max) is the point in time when the odt resistance is fully on. both are measured from odtlon. minimum rtt turn - off time (taof min) is the point in time when the device starts to turn off the odt resistance. maximum rtt turn off time (taof max) is the point in time when the on - die termination has reached high impedance. both are measured from odtloff. when odt is asserted, it must remain high until odth4 i s satisfied. if a write command is registered by the sdram with odt high, then odt must remain high until odth4 (bl=4) or odth8 (bl=8) after the write command. odth4 and odth8 are measured from odt registered high to odt registered low or from the registra tion of a write command until odt is registered low . l odt during reads as the ddr3 sdram cannot terminate and drive at the same time, rtt must be disabled at least half a clock cycle before the read preamble by driving the odt pin low appropriately. rtt may not be enabled until the end of the post - amble as shown in the following figure. dram turns on the termination when it stops driving which is determined by thz. if dram stops driving early (i.e. thz is early), then taonmin time may apply. if dram stops driving late (i.e. thz is late), then dram complies with taonmax timing. note that odt may be disabled earlier before the read and enabled later after the read than shown in this example . . confidential - 48/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 22 . odt must be disabled externally during reads by driv ing odt low (cl=6; al=cl - 1=5; rl=al+cl=11; cwl=5; odtlon=cwl+al - 2=8; odtloff=cwl+al - 2=8) nop read nop nop nop nop nop nop nop nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck t12 t13 t14 nop nop nop don't care transitioning data t15 nop odt t16 t17 nop nop odtlon = cwl + al - 2 odtloff = cwl + al - 2 rl = al + cl t aof (min) t aof (max) t aon (max) valid rtt rtt_nom rtt_nom din b din b+1 din b+2 din b+3 din b+4 din b+5 din b+6 dq command address dqs, dqs# din b+7 l dynamic odt in certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the ddr3 sdram can be changed without issuing an mrs command. this requirement is supported by the ?ynamic odt?feature as described as follows: functional description the dynamic odt mode is enabled if bit (a9) or (a10) of mr2 is set to 1 ? the function is described as follows: two rtt values are available: rtt_nom and rtt_wr. - the value for rtt_nom is preselected via bits a[9,6,2] in mr1. - the value for rtt_wr is preselected via bits a[10,9] in mr2. during operation without write comm ands, the termination is controlled as follows: - nominal termination strength rtt_nom is selected. - termination on/off timing is controlled via odt pin and latencies odtlon and odtloff. when a write comma nd (wr, wra, wrs4, wrs8, wras4, wras8) is registe red, and if dynamic odt is enabled, the termination is controlled as follows: - a latency odtlcnw after the write command, termination strength rtt_wr is selected. - a latency odtlcwn8 (for bl8, fixed by mrs or selected otf) or odtlcwn4 (for bc4, fixed by mrs or selected otf) after the write command, termination strength rtt_nom is selected. - termination on/off timing is controlled via odt pin and odtlon, odtloff. the following table shows latencies and timing parameters which are relevant for the on - die termination control in dynamic odt mode. the dynamic odt feature is not supported at dll - off mode. user must use mrs command to set rtt_wr, mr2 [a10,a9 = [0,0], to disable dynamic odt externally. when odt is asserted, it must remain high until odth4 is s atisfied. if a write command is registered by the sdram with odt high, then odt must remain high until odth4 (bl=4) or odth8 (bl=8) after the write command. odth4 and odth8 are measured from odt registered high to odt registered low or from the registratio n of write command until odt is register low. confidential - 49/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
table 27. latencies and timing parameters relevant for dynamic odt name and description abbr. defined from defined to definition for all ddr3 speed pin unit odt turn - on latency odtlon registering extern al odt signal high turning termination on odtlon=wl -2 tck odt turn - off latency odtloff registering external odt signal low turning termination off odtloff=wl -2 tck odt latency for changing from rtt_nom to rtt_wr odtlcnw registering external write command change rtt strength from rtt_nom to rtt_wr odtlcnw=wl -2 tck odt latency for change from rtt_wr to rtt_nom (bl=4) odtlcwn4 registering external write command change rtt strength from rtt_wr to rtt_nom odtlcwn4=4+odtloff tck odt latency for change from rt t_wr to rtt_nom (bl=8) odtlcwn8 registering external write command change rtt strength from rtt_wr to rtt_nom odtlcwn8=6+odtloff tck (avg) minimum odt high time after odt a ssertion odth4 registering odt high odt registered low odth4=4 tck (avg) minimum o dt high time after write (bl=4) odth4 registering write with odt high odt registered low odth4=4 tck (avg) minimum odt high time after write (bl=8) odth8 registering write with odt high odt register low odth8=6 tck (avg) rtt change skew tadc odtlcnw odtl cwn rtt valid tadc(min)=0.3tck(avg) tadc(max)=0.7tck(avg) tck (avg) note 1 : taof, nom and tadc,nom are 0.5tck (effectively adding half a clock cycle to odtloff, odtcnw, and odtlcwn) l asynchronous odt mode asynchronous odt mode is selected when dram runs in dllon mode, but dll is temporarily disabled (i.e. frozen) in precharge power - down (by mr0 bit a12). based on the power down mode definitions, this is currently precharge power down mode if dll is disabled during precharge power down by mr0 bit a12. in a synchronous odt timing mode, internal odt command is not delayed by additive latency (al) relative to the external odt command. in asynchronous odt mode, the following timing parameters apply: taonpd min/max, taofpd min/max. minimum rtt turn - on time (taonp d min) is the point in time when the device termination circuit leaves high impedance state and odt resistance begins to turn on. maximum rtt turn on time (taonpd max) is the point in time when the odt resistance is fully on. taonpdmin and taonpdmax are me asured from odt being sampled high. minimum rtt turn - off time (taofpdmin) is the point in time when the devices termination circuit starts to turn off the odt resistance. maximum odt turn off time (taofpdmax) is the point in time when the on - die termination has reached high imped ance. taofpdmin and taofpdmax are measured from odt being sample low. table 28. odt timing parameters for power down (with dll frozen) entry and exit description min max odt to rtt turn - on delay min{ odtlon * tck + taonmin; tao npdmin } min{ (wl - 2) * tck + taonmin; taonpdmin } max{ odtlon * tck + taonmax; taonpdmax } max{ (wl - 2) * tck + taonmax; taonpfmax } odt to rtt turn - off delay min{ odtloff * tck + taofmin; taofpdmin } min{ (wl - 2) * tck + taofmin; taofpdmin } max{ odt loff * tck + taofmax; taofpdmax } max{ (wl - 2) * tck + taofmax; taofpdmax } tanpd wl - 1 confidential - 50/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l synchronous to asynchronous odt mode transition during power-down entry if dll is selected to be frozen in precharge power down mode by the setting of bit a12 in mr0 to 0, there is a transition period around power down entry, where the ddr3 sdram may show either synchronous or asynchronous odt behavior. the transition period is defined by the pa rameters tanpd and tcpded(min). tanpd is equal to (wl - 1) and is coun ted backwards in time from the clock cycle whe re cke is first registered low. tcpded(min) starts with the clock cycle where cke is first registered low. the transition period begins with the starting point of tanpd and terminates at the end point of tcpded (min). if there is a refresh command in progress while cke goes low, then the transition period ends at the later one of trfc(min) after the refresh command and the end point of tcpded(min). please note that the actual starting point at tanpd is excluded f rom the transition period, and the actual end point at tcpded(min) and trfc(min, respectively, are included in the transition period. odt assertion during the transition period may result in an rtt changes as early as the smaller of taonpdmin and (odtlon*t ck+taonmin) and as late as the larger of taonpdmax and (odtlon*tck+taonmax). odt de - assertion during the transition period may result in an rtt change as early as the smaller of taofpdmin and (odtloff*tck+taofmin) and as late as the larger of taofpdmax and (odtloff*tck+taofmax). note that, if al has a large value, the range where rtt is uncertain becomes quite large. the following figure shows the three different cases: odt_a, synchronous behavior before tanpd; odt_b has a state change during the transition period; odt_c shows a state change after the transition period. l asynchronous to synchronous odt mode transition during power-down exit if dll is selected to be frozen in precharge power down mode by the setting of bit a12 in mr0 to 0, there is also a transition period around power down exit, where either synchronous or asynchronous response to a change in odt must be expected from the ddr3 sdram. this transition period starts tanpd before cke is first registered high, and ends txpdll after cke is first registered high. tanpd is equal to (wl - 1) and is counted (backwards) from the clock cycle where cke is first registered high. odt assertion during the transition period may result in an rtt change as early as the smaller of taonpdmin and (odtlon* tck+tao nmin) and as late as the larger of taonpdmax and (odtlon*tck+taonmax). odt de - assertion during the transition period may result in an rtt change as early as the smaller of taofpdmin and (odtloff*tck+taofmin) and as late as the larger of taofpdmax and (odtoff*tck+taofmax). note that if al has a large value, the range where rtt is uncertain becomes quite large. the following figure shows the three different cases: odt_c, asynchronous response before tanpd; odt_b has a state change of odt during the transition period; odt_a shows a state change of odt after the transition period with synchronous response. l asynchronous to synchronous odt mode during short cke high and short cke low periods if the total time in precharge power down state or idle state is very s hort, the transition periods for pd entry and pd exit may overlap. in this case, the response of the ddr3 sdrams rtt to a change in odt state at the input may be synchronous or asynchronous from the state of the pd entry transition period to the end of the pd exit transition period (even if the entry ends later than the exit period). if the total time in idle state is very short, the transition periods for pd exit and pd entry may overlap. in this case, the response of the ddr3 sdrams rtt to a change in odt state at the input may be synchronous or asynchronous from the state of the pd exit transition period to the end of the pd entry transition period. note that in the following figure, it is assumed that there was no refresh command in progress when idle state was entered. confidential - 51/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
zq calibration commands l zq calibration description zq calibration command is used to calibrate dram ron and odt values. ddr3 sdram needs longer time to calibrate output driver and on - die termination circuits at initialization and relati vely smaller time to perform periodic calibrations. zqcl command is used to perform the initial calibration during power - up initialization sequence. this command may be issued at any time by the controller depending on the system environment. zqcl command triggers the calibration engine inside the dram and once calibration is achieved the calibrated values are transferred from calibration engine to dram io which gets reflected as updated output driver and on - die termination values. the first zqcl command is sued after reset is allowed a timing period of tzqinit to perform the full calibration and the transfer of values. all other zqcl commands except the first zqcl command issued after reset is allowed a timing period of tzqoper. zqcs command is used to perfo rm periodic calibrations to account for voltage and temperature variations. a shorter timing window is provided to perform the calibration and transfer of values as defined by timing parameter tzqcs. no other activities should be performed on the dram chan nel by the controller for the duration of tzqinit, tzqoper, or tzqcs. the quiet time on the dram channel allows calibration of output driver and on - die termination values. once dram calibration is achieved, the dram should disable zq current consumption pa th to reduce power. all banks must be precharged and trp met before zqcl or zqcs commands are issued by the controller. zq calibration commands can also be issued in parallel to dll lock time when coming out of self refresh. upon self - refresh exit, ddr3/l sdram will not perform an io calibration without an explicit zq calibration command. the earliest possible time for zq calibration command (short or long) after self refresh exit is txs. in systems that share the zq resistor between devices, the controller must not allow any overlap of tzqoper, tzqinit, or tzqcs between ranks. figure 23. zq calibration timing ck# t1 ta0 ta1 ta2 ta3 t0 ck cke nop zqcl nop valid t zqinit or t zqoper don't care time break valid tb0 tb1 zqcs nop t zqcs tc0 tc1 nop nop address notes: 1. cke must be continuously registered high during the calibration procedure. 2. on-die termination must be disabled via the odt signal or mrs during the calibration procedure. 3. all devices connected to the dq bus should be high impedance during the calibration procedure. tc2 nop valid valid valid valid a10 valid valid valid valid valid valid notes 1 odt valid valid valid notes 2 hi-z activities hi-z notes 3 command dq bus activities notes 1 notes 2 notes 3 confidential - 52/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l zq external resistor value, tolerance, and capacitive loading in order to use the zq calibration function, a 240 ohm +/ - 1% tolerance external resistor connected between the zq pin and ground. the single resistor can be used for each sdram or one resistor can be shared between two sdrams if the zq calibration timings for each sdram do not overlap. the total capacitiv e loading on the zq pin must be limited. - single-ended requirements for differential signals each individual component of a differential signal (ck, ck# , dqs or dqs# ) has also to comply with certain requirements for single - ended signals. ck and ck# have to approximately reach vsehmin / vselmax (approximately equal to the ac - levels (vih(ac) / vil(ac)) for add/cmd signals ) in every half - cycle. dqs , dqs# have to reach vsehmin / vselmax (approximately the ac - levels (vih(ac) / vil(ac)) for dq signals) in ever y half - cycle proceeding and following a valid transition. note that the applicable ac - levels for add/cmd and dq? might be different per speed - bin etc. e.g., if vih150(ac)/vil150(ac) is used for add/cmd signals, then these ac - levels apply also for the sin gle - ended signals ck and ck# . table 2 9. single-ended levels for ck, dqs, ck#, dqs# symbol parameter min. max. unit note vseh single - ended high level for strobes (v dd / 2) + 0.175 - v 1 ~3 single - ended high level for ck, ck# (v dd / 2) + 0.175 - v 1~3 vsel single - ended low level for strobes - (v dd / 2) - 0.175 v 1~3 single - ended low level for ck, ck# - (v dd / 2) - 0.175 v 1~3 note 1 : for ck, ck# use vih/vil(ac) of add/cmd; for strobes (dqs, dqs#) use vih/vil(ac) of dqs. note 2 : vih(ac)/vil(ac) for dq s is based on vrefdq; vih(ac)/vil(ac) for add/cmd is based on vrefca; if a reduced ac - high or ac - low level is used for a signal group, then the reduced level applies also here . note 3 : these values are not defined, however the single - ended signals ck, ck#, dqs, dqs # need to be within the respective limits (vih(dc) max, vil(dc)min) for single - ended signals as well as the limitations for overshoot and undershoot. - differential input cross point voltage to guarantee tight setup and hold times as well as ou tput skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (ck, ck # and dqs, dqs # ) must meet the requirements in the following table. the differential input cross point voltage vix is measured from the actual cross point of true and complete signal to the midlevel between of vdd and vss. table 30. cross point voltage for differential input signals (ck, dqs) symbol parameter min. max. unit note vix(ck) differential input cross point voltage relative to vd d/2 for ck, ck# - 150 150 mv 2 - 175 175 mv 1 vix(dqs) differential input cross point voltage relative to vdd/2 for dqs, dqs# - 150 150 mv 2 note 1 : extended range for vix is only allowed for clock and if single - ended clock input signals ck and ck# ar e monotonic with a single - ended swing vsel / vseh of at least vdd/2 +/ - 250 mv, and when the differential slew rate of ck - ck# is larger than 3 v/ns. note 2 : the relation between vix min/max and vsel/vseh should satisfy following. (vdd/2) + vix (min) - vsel R 25mv vseh - ((vdd/2) + vix (max)) R 25mv confidential - 53/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
- slew rate definition for differential input signals input slew rate for differential signals (ck, ck# and dqs, dqs#) are defined and measured as shown below. table 31. differential input slew rate definition description measured defined by from to differential input slew rate for rising edge (ck , ck# and dqs , dqs# ) vildiffmax vihdiffmin [vihdiffmin - vildiffmax] / deltatrdiff differential input slew rate for falling edge (ck , ck# and dqs , dqs# ) vihdiffmin vildiffmax [vihdiffmin - vildiffmax] / deltatfdiff note: the differential signal (i.e., ck , ck# and dqs , dqs#) must be linear between these thresholds. table 32. single-ended ac and dc output levels symbol parameter - 12 unit note v oh (dc) dc output high measurement level (for iv curve linearity) 0.8 x v ddq v v om (dc) dc output mid measurement level (for iv curve linearity) 0.5 x v ddq v v ol (dc) dc output low measurement level (for iv curve linearity) 0.2 x v ddq v v oh (ac) ac output high measurement lev el (for output sr) v tt + 0.1 x v ddq v 1 v ol (ac) ac output low measurement level (for output sr) v tt - 0.1 x v ddq v 1 note 1: the swing of 0.1 vddq is based on approximately 50% of the static single - ended output high or low swing with a driver impedan ce of 40 and an effective test load of 25 to vtt = vddq/2. table 33. differential ac and dc output levels symbol parameter - 12 unit note v ohdiff (ac) ac differential output high measurement level (for output sr) + 0.2 x v ddq v 1 v oldiff (ac) ac diff erential output low measurement level (for output sr) - 0.2 x v ddq v 1 note 1 : the swing of 0.2 vddq is based on approximately 50% of the static single - ended output high or low swing with a driver impedance of 40 and an effective test load of 25 t o vtt = vddq/2 at each of the differential outputs. confidential - 54/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
- single ended output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between vol(ac) and voh(ac) for single ended signa ls as shown in table . table 34. output slew rate definition (single-ended ) description measured defined by from to single - ended output slew rate for rising edge vol(ac) voh(ac) [voh(ac) - vol(ac)] / deltatrse single - ended output slew rate for fall in g edge voh(ac) vol(ac) [voh(ac) - vol(ac)] / deltat f se note: output slew rate is verified by design and characterization, and may not be subject to production test. table 35. output slew rate (single-ended) symbol parameter -1 2 unit min. max. srq se single - ended output slew rate 2.5 5 v/ns description: sr: slew rate q: query output (like in dq, which stands for data - in, query - output) se: single - ended signals for ron = rzq/7 setting - differential output slew rate with the reference load for tim ing measurements, output slew rate for falling and rising edges is defined and measured between voldiff(ac) and vohdiff(ac) for differential signals as shown in table. table 36. output slew rate definition (differential) description measured defined by from to differential output slew rate for rising edge voldiff(ac) vohdiff(ac) [vohdiff(ac) - voldiff(ac)] / deltatrdiff differential output slew rate for fall ing edge vohdiff(ac) voldiff(ac) [vohdiff(ac) - voldiff(ac)] / deltat f diff note: output slew rate is verified by design and characterization, and may not be subject to production test . table 37. output slew rate (differential) symbol parameter -12 unit min. max. srq diff differential output slew rate 5 10 v/ns description: sr: slew rate q: query output (like in dq, which stands for data - in, query - output) diff: differential signals for ron = rzq/7 setting confidential - 55/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
l reference load for ac timing and output slew rate the following figure represents the effective reference load of 25 ohms used in de fining the relevant ac timing parameters of the device as well as output slew rate measurements. it is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. system designers should use ibis or other simulation tools to correlate the timing reference load to a system environment. manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester elect ronics. figure 24. reference load for ac timing and output slew rate dut dq dqs dqs# vddq ck, ck# 25 ohm vtt = vddq/2 table 38. ac overshoot/undershoot specification for address and control pins parameter -1 2 unit maximum peak amplitude allowed for overshoot area. 0.4 v maximum peak amplitude allowed for undershoot area. 0.4 v maximum overshoot area above vdd 0.33 v- ns maximum undershoot area below vss 0.33 v- ns table 39. ac overshoot/undershoot specification for clock, data, strobe and mask parameter -1 2 uni t maximum peak amplitude allowed for overshoot area. 0.4 v maximum peak amplitude allowed for undershoot area. 0.4 v maximum overshoot area above vdd 0.1 3 v- ns maximum undershoot area below vss 0.1 3 v- ns confidential - 56/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
- address / command setup, hold and derating for all input signals the total tis (setup time) and tih (hold time) required is calculated by adding the data sheet tis(base) and tih(base) and tih(base) value to the delta tis and delta tih derating value respectively. example: tis (total setup time) = tis(base) + delta tis . setup (tis) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vih(ac)min. setup (tis) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vil(ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded vref(dc) to ac region, use nominal slew rate for derating value. if the actual signal is la ter than the nominal slew rate line anywhere between shaded vref(dc) to ac region, the slew rate of the tangent line to the actual signal from the ac level to dc level is used for derating value. hold (tih) nominal slew rate for a rising signal is define d as the slew rate between the last crossing of vil(dc)max and the first crossing of vref(dc). hold (tih) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc)min and the first crossing of vref(dc). if the actual signal is always later than the nominal slew rate line between shaded dc to vref(dc) region, use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded dc to vref(dc) region, the slew rate of a tangent line to the actual signal from the dc level to vref(dc) level is used for derating value. for a valid transition the input signal has to remain above/below vih/il(ac) for some time tvac. although for slow slew rates the total se tup time might be negative (i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach vih/il(ac). table 40. add/cmd setup and hold base - values for 1v/ns symbol reference -1 2 unit t is (base) ac175 v ih/l (ac) 45 ps t is (base) ac150 v ih/l (ac) 170 ps t ih (base) dc100 v ih/l (dc) 120 ps note 1 : (ac/dc referenced for 1v/ns address/command slew rate and 2 v/ns differential ck - ck# slew rate) n ote 2 : the tis(base) ac150 specifications are adjusted from the tis(base) specification by adding an additional 100ps of derating to accommodate for the lower alternate threshold of 150 mv and another 25 ps to account for the earlier reference point [(175 mv - 150 mv) / 1 v/ns]. table 41. derating values ddr3-1600 tis/tih ?( ac175) t i s , t ih derating in [ps] ac/dc based ac175 threshold - > v ih (ac)=v ref (dc)+175mv, v il (ac)=v ref (dc) - 175mv ck, ck# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd /ad d slew rate v/ns 2.0 88 50 88 50 88 50 96 58 104 66 112 74 120 84 128 100 1.5 59 34 59 34 59 34 67 42 75 50 83 58 91 68 99 84 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 -2 -4 -2 -4 -2 -4 6 4 14 12 22 20 30 30 38 46 0.8 -6 - 10 -6 - 10 -6 - 10 2 -2 10 6 18 14 26 24 34 40 0.7 - 11 - 16 - 11 - 16 - 11 - 16 -3 -8 5 0 13 8 21 18 29 34 0.6 - 17 - 26 - 17 - 26 - 17 - 26 -9 - 18 -1 - 10 7 -2 15 8 23 24 0.5 - 35 - 40 - 35 - 40 - 35 - 40 - 27 - 32 - 19 - 24 - 11 - 16 -2 -6 5 10 0.4 - 62 - 60 - 62 - 60 - 62 - 60 - 54 - 52 - 46 - 44 - 38 - 36 - 30 - 26 - 22 - 10 confidential - 57/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
table 42. derating values ddr3-1600 tis/tih ?( ac150) t i s , t ih derating in [ps] ac/dc based alternate ac15 0 threshold - > v ih (ac)=v ref (dc)+1 50 mv, v il (ac)=v ref (dc) -1 50mv ck, ck# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd /ad d slew rate v/ns 2.0 75 50 75 50 75 50 83 58 91 66 99 74 107 84 115 100 1.5 50 34 50 34 50 34 58 42 66 50 74 58 82 68 90 84 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 0 -4 0 -4 0 -4 8 4 16 12 24 20 32 30 40 46 0.8 0 - 10 0 - 10 0 - 10 8 -2 16 6 24 14 32 24 40 40 0.7 0 - 16 0 - 16 0 - 16 8 -8 16 0 24 8 32 18 40 34 0.6 -1 - 26 -1 - 26 -1 - 26 7 - 18 15 - 10 23 -2 31 8 39 24 0.5 - 10 - 40 - 10 - 40 - 10 - 40 -2 - 32 6 - 24 14 - 16 22 -6 30 10 0.4 - 25 -60 - 25 - 60 - 25 - 60 - 17 - 52 -9 - 44 -1 - 36 7 - 26 15 - 10 confidential - 58/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
- data setup, hold, and slew rate de-rating for all input signals the total tds (setup time) and tdh (hold time) required is calculated by adding the data sheet tds(base) and tdh(base) value to the tds and tdh derating value respectively. example: tds (total setup time) = tds(base) + tds. setup (tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vih(ac)min. setup (tds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vil(ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded vref(dc) to ac regi on, use nominal slew rate for derating value. if the actual signal is later than the nominal slew rate line anywhere between shaded vref(dc) to ac region, the slew rate of the tangent line to the actual signal from the ac level to dc level is used for d erating value. hold (tdh) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the first crossing of vref(dc). hold (tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc)min and the first crossing of vref(dc). if the actual signal is always later than the nominal slew rate line between shaded dc level to vref(dc) region, use nominal slew rate for derating value. if the actual signal is earlier t han the nominal slew rate line anywhere between shaded dc to vref(dc) region, the slew rate of a tangent line to the actual signal from the dc level to vref(dc) level is used for derating value. for a valid transition the input signal has to remain above /below vih/il(ac) for some time tvac. although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is still required to comp lete the transition and reach vih/il(ac). for slew rates in between the values listed in the following tables, the derating values may be obtained by linear interpolation. these values are typically not subject to production test. they are verified by desi gn and characterization. table 43. data setup and hold base - values for 1v/ns symbol reference -1 2 unit t ds (base) ac150 v ih/l (ac) 10 ps t dh (base) dc100 v ih/l (d c) 45 ps note 1: (ac/dc referenced for 1 v/ns dq - slew rate and 2 v/ns differential dqs slew rate) table 44. derating values for ddr3-1600 tds/tdh ?(ac150) t d s , t dh derating in [ps] ac/dc based alternate ac150 threshold - > v ih (ac)=v ref (dc)+150mv, v il (ac)=v ref (dc) - 150mv dqs, dqs# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh dq slew rate v/ns 2.0 75 50 75 50 75 50 - - - - - - - - - - 1.5 50 34 50 34 50 34 58 42 - - - - - - - - 1.0 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - 0 -4 0 -4 8 4 16 12 24 20 - - - - 0.8 - - - - 0 - 10 8 -2 16 6 24 14 32 24 - - 0.7 - - - - - - 8 -8 16 0 24 8 32 18 40 34 0.6 - - - - - - - - 15 - 10 23 -2 31 8 39 24 0.5 - - - - - - - - - - 14 - 16 22 -6 30 10 0.4 - - - - - - - - - - - - 7 - 26 15 - 10 confidential - 59/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
timing waveforms figure 2 5. mpr readout of predefined pattern,bl8 fixed burst order, single readout don't care time break mrs prea read nop nop nop nop nop nop nop nop mrs t rp notes: 1. rd with bl8 either by mrs or otf. 2. memory controller must drive 0 on a[2:0]. t0 ta tb0 tb1 tc0 tc1 tc2 tc3 tc4 tc5 tc6 tc7 ck# ck ba a[1:0] a[2] a[11] a12, bc# a[9:3] a10, ap tc8 tc9 td mrs mrs valid t mod notes 1 t mprr t mod 3 valid 3 0 0 valid 1 0 0 00 valid 00 0 valid 0 0 valid 0 0 valid 0 0 valid 0 a[14:13] dq 1 rl notes 2 notes 2 dqs, dqs# command figure 2 6. mpr readout of predefined pattern,bl8 fixed burst order, back to back radout don't care time break mrs prea read read nop nop nop nop nop nop nop nop t rp notes: 1. rd with bl8 either by mrs or otf. 2. memory controller must drive 0 on a[2:0]. t0 ta tb tc0 tc1 tc2 tc3 tc4 tc5 tc6 tc7 tc8 ck# ck ba a[1:0] a[2] a[11] a12, bc# a[9:3] a10, ap tc9 tc10 td nop mrs valid t mod notes 1 t mprr t mod 3 valid 3 0 0 valid 1 0 0 00 valid 00 0 valid 0 0 valid 0 0 valid 0 0 valid 0 a[14:13] dq 1 rl notes 2 notes 2 notes 1 t ccd valid 0 0 valid valid valid valid valid notes 2 notes 1 notes 1 notes 2 dqs, dqs# command rl confidential - 60/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 2 7. mpr readout of predefined pattern,bc4 lower nibble then upper nibble don't care time break mrs prea read read nop nop nop nop nop nop nop mrs t rp notes: 1. rd with bc4 either by mrs or otf. 2. memory controller must drive 0 on a[1:0]. 3. a[2]=0 selects lower 4 nibble bits 0....3. 4. a[2]=1 selects upper 4 nibble bits 4....7. t0 ta tb tc0 tc1 tc2 tc3 tc4 tc5 tc6 tc7 tc8 ck# ck ba a[1:0] a[2] a[11] a12, bc# a[9:3] a10, ap tc9 tc10 td nop nop valid t mod notes 1 t mprr t mod 3 valid 3 0 0 valid 1 0 0 00 valid 00 0 valid 0 0 valid 0 0 valid 0 0 valid 0 a[14:13] dq 1 rl notes 2 notes 3 notes 1 t ccd valid 0 1 valid valid valid valid valid notes 2 notes 1 notes 1 notes 4 dqs, dqs# command rl figure 2 8. mpr readout of predefined pattern,bc4 upper nibble then lower nibble don't care time break mrs prea read read nop nop nop nop nop nop nop mrs t rp notes: 1. rd with bc4 either by mrs or otf. 2. memory controller must drive 0 on a[1:0]. 3. a[2]=0 selects lower 4 nibble bits 0....3. 4. a[2]=1 selects upper 4 nibble bits 4....7. t0 ta tb tc0 tc1 tc2 tc3 tc4 tc5 tc6 tc7 tc8 ck# ck ba a[1:0] a[2] a[11] a12, bc# a[9:3] a10, ap tc9 tc10 td nop nop valid t mod notes 1 t mprr t mod 3 valid 3 0 0 valid 1 1 0 00 valid 00 0 valid 0 0 valid 0 0 valid 0 0 valid 0 a[14:13] dq 1 rl notes 2 notes 4 notes 1 t ccd valid 0 0 valid valid valid valid valid notes 2 notes 1 notes 1 notes 3 dqs, dqs# command rl confidential - 61/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 29 . read (bl8) to read (bl8) nop read nop nop read nop nop nop nop nop nop nop notes: 1. bl8, rl = 5 (cl = 5, al = 0) 2. dout n (or b) = data-out from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0 = 00] or mr0[a1:0 = 01] and a12 = 1 during read commands at t0 and t4. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck dq t12 t13 t14 nop nop nop t ccd notes 3 notes 4 bank, col n bank, col b dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 dout b dout b+1 dout b+2 dout b+3 dout b+4 dout b+5 dout b+6 dout b+7 t rpst t rpre rl = 5 rl = 5 don't care transitioning data notes 2 dqs, dqs# address command figure 3 0. nonconsecutive read (bl8) to read (bl8) nop read nop nop nop read nop nop nop nop nop nop notes: 1. bl8, rl = 5 (cl = 5, al = 0), tccd=5 2. dout n (or b) = data-out from column n (or column b) 3. nop commands are shown for ease of illustration; other commands may be valid at these times 4. bl8 setting activated by either mr0[a1:0 = 00] or mr0[a1:0 = 01] and a12 = 1 during read commands at t0 and t4 5. dqs-dqs# is held logic low at t9 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck dq t12 t13 t14 nop nop nop t ccd = 5 notes 3 notes 4 bank, col n bank, col b do n do b t rpst t rpre rl = 5 rl = 5 don't care transitioning data notes 2 dqs, dqs# address command notes 5 figure 3 1. read (bl4) to read (bl4) nop read nop nop read nop nop nop nop nop nop nop notes: 1. bc4, rl = 5 (cl = 5, al = 0) 2. dout n (or b) = data-out from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by either mr0[a1:0 = 10] or mr0[a1:0 = 01] and a12 = 0 during read commands at t0 and t4. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck dq t12 t13 t14 nop nop nop t ccd notes 3 notes 4 bank, col n bank, col b dout n dout n+1 dout n+2 dout n+3 dout b dout b+1 dout b+2 dout b+3 t rpre rl = 5 rl = 5 don't care transitioning data notes 2 dqs, dqs# address command t rpst t rpst t rpre confidential - 62/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 3 2. read (bl8) to write (bl8) nop read nop nop nop read nop nop nop nop nop nop notes: 1. bl8, rl = 5 (cl = 5, al = 0), tccd=5 2. dout n (or b) = data-out from column n (or column b) 3. nop commands are shown for ease of illustration; other commands may be valid at these times 4. bl8 setting activated by either mr0[a1:0 = 00] or mr0[a1:0 = 01] and a12 = 1 during read commands at t0 and t4 5. dqs-dqs# is held logic low at t9 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck dq t12 t13 t14 nop nop nop t ccd = 5 notes 3 notes 4 bank, col n bank, col b do n do b t rpst t rpre rl = 5 rl = 5 don't care transitioning data notes 2 dqs, dqs# address command notes 5 figure 3 3. read (bl4) to write (bl4) otf nop read nop nop write nop nop nop nop nop nop nop notes: 1. bc4, rl = 5 (cl = 5, al = 0), wl = 5 (cwl = 5, al = 0) 2. dout n = data-out from column, din b = data-in from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[a1:0 = 01] and a12 = 0 during read command at t0 and write command at t4. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck dq t12 t13 t14 nop nop nop read to write command delay = rl + tccd/2 + 2tck - wl notes 3 notes 4 bank, col n bank, col b dout n dout n+1 dout n+2 dout n+3 din b din b+1 din b+2 din b+3 t rpre rl = 5 wl = 5 don't care transitioning data notes 2 dqs, dqs# address command t rpst t wpre t15 nop t wpst 4 clocks t wr t wtr figure 3 4. read (bl8) to read (bl4) otf nop read nop nop read nop nop nop nop nop nop nop notes: 1. rl = 5 (cl = 5, al = 0) 2. dout n (or b) = data-out from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0[a1:0 = 01] and a12 = 1 during read command at t0. bc4 setting activated by mr0[a1:0 = 01] and a12 = 0 during read command at t4. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck dq t12 t13 t14 nop nop nop t ccd notes 3 notes 4 bank, col n bank, col b dout n dout n+1 dout n+2 dout n+3 dout b dout b+1 dout b+2 dout b+3 t rpre rl = 5 rl = 5 don't care transitioning data notes 2 dqs, dqs# address command t rpst dout n+4 dout n+5 dout n+6 dout n+7 confidential - 63/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 3 5. read (bl4) to read (bl8) otf nop read nop nop read nop nop nop nop nop nop nop notes: 1. rl = 5 (cl = 5, al = 0) 2. dout n (or b) = data-out from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[a1:0 = 01] and a12 = 0 during read command at t0. bl8 setting activated by mr0[a1:0 = 01] and a12 = 1 during read command at t4. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck dq t12 t13 t14 nop nop nop t ccd notes 3 notes 4 bank, col n bank, col b dout n dout n+1 dout n+2 dout n+3 dout b+4 dout b+5 dout b+6 dout b+7 t rpre rl = 5 rl = 5 don't care transitioning data notes 2 dqs, dqs# address command t rpst dout b dout b+1 dout b+2 dout b+3 t rpst t rpre figure 36. r ead (bc4) to write (bl8) otf nop read nop nop write nop nop nop nop nop nop nop notes: 1. bc4, rl = 5 (cl = 5, al = 0), wl = 5 (cwl = 5, al = 0) 2. dout n = data-out from column, din b = data-in from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[a1:0 = 01] and a12 = 0 during read command at t0 and write command at t4. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck dq t12 t13 t14 nop nop nop read to write command delay = rl + tccd/2 + 2tck - wl notes 3 notes 4 bank, col n bank, col b dout n dout n+1 dout n+2 dout n+3 din b din b+1 din b+2 din b+3 t rpre rl = 5 wl = 5 don't care transitioning data notes 2 dqs, dqs# address command t rpst t wpre t15 nop t wpst 4 clocks t wr t wtr din b+4 din b+5 din b+6 din b+7 figure 37 . read (bl8) to write (bl4) otf nop read nop nop nop nop write nop nop nop nop nop notes: 1. rl = 5 (cl = 5, al = 0), wl = 5 (cwl= 5, al = 0) 2. dout n = data-out from column, din b = data-in from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0[a1:0 = 01] and a12 = 1 during read command at t0. bc4 setting activated by mr0[a1:0 = 01] and a12 = 0 during write command at t6. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck dq t12 t13 t14 nop nop nop read to write command delay = rl + tccd + 2tck - wl notes 3 notes 4 bank, col n bank, col b dout n dout n+1 dout n+2 dout n+3 din b din b+1 din b+2 din b+3 t rpre rl = 5 wl = 5 don't care transitioning data notes 2 dqs, dqs# address command t rpst t wpre t15 nop t wpst dout n+4 dout n+5 dout n+6 dout n+7 4 clocks t wr t wtr confidential - 64/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 38. read to precharge, rl = 5, al = 0, cl = 5, trtp = 4, trp = 5 read nop nop nop nop pre nop nop nop nop act nop notes: 1. rl = 5 (cl = 5, al = 0) 2. dout n = data-out from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. the example assumes tras.min is satisfied at precharge command time (t5) and that trc.min is satisfied at the next active command time (t10). t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck dq t12 t13 t14 nop nop nop rl = al + cl bank a, (or all) bank a, row b do n do n+1 do n+2 do n+3 don't care transitioning data t15 nop t rp t rtp bank a, col n dq do n do n+1 do n+2 do n+3 bl4 operation: bl8 operation: do n+4 do n+5 do n+6 do n+7 dqs, dqs# dqs, dqs# address command figure 3 9. read to precharge, rl = 8, al = cl-2, cl = 5, trtp = 6, trp = 5 read nop nop nop nop nop nop nop nop nop pre nop notes: 1. rl = 8 (cl = 5, al = cl - 2) 2. dout n = data-out from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. the example assumes tras.min is satisfied at precharge command time (t10) and that trc.min is satisfied at the next active command time (t15). t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck dq t12 t13 t14 nop nop nop al = cl - 2 = 3 bank a, (or all) do n do n+1 do n+2 do n+3 don't care transitioning data t15 act t rtp bank a, col n dq do n do n+1 do n+2 do n+3 bl4 operation: bl8 operation: do n+4 do n+5 do n+6 do n+7 bank a, row b cl = 5 t rp dqs, dqs# dqs, dqs# address command confidential - 65/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 4 0. write timing definition and parameters nop write nop nop nop nop nop nop nop nop nop notes: 1. bl8, wl = 5 (al = 0, cwl = 5) 2. din n = data-in from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0 = 00] or mr0[a1:0 = 01] and a12 = 1 during write command at t0. 5. tdqss must be met at each rising clock edge. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 ck# ck dq wl = al + cwl din n din n+2 din n+3 don't care transitioning data bank col n dm notes 3 notes 4 notes 2 t dqss(min) t wpre(min) t dqsh(min) t dqsl t dqss t dsh t dqsh t dqsl t dqsh t dqsl t dqsh t dqsl t dqsh t dqsl(min) t dsh t dsh t wpst(min) t dss t dss t dss t dss t dss din n+4 din n+6 din n+7 dq din n din n+2 din n+3 dm notes 2 t dqss(nominal) t wpre(min) t dqsh(min) t dqsl t dsh t dqsh t dqsl t dqsh t dqsl t dqsh t dqsl t dqsh t dqsl(min) t dsh t dsh t dsh t wpst(min) t dss t dss t dss t dss t dss din n+4 din n+6 din n+7 t dsh dq din n din n+2 din n+3 dm notes 2 t dqss(max) t wpre(min) t dqsh(min) t dqsl t dsh t dqsh t dqsl t dqsh t dqsl t dqsh t dqsl t dqsh t dqsl(min) t dsh t dsh t dsh t wpst(min) t dss t dss t dss t dss t dss din n+4 din n+6 din n+7 t dqss command address dqs, dqs# dqs, dqs# dqs, dqs# confidential - 66/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 4 1. write burst operation wl = 5 (al = 0, cwl = 5, bl8) nop write nop nop nop nop nop nop nop nop nop notes: 1. bl8, wl = 5; al = 0, cwl = 5. 2. din n = data-in from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0 = 00] or mr0[a1:0 = 01] and a12 = 1 during write command at t0. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 ck# ck dq wl = al + cwl din n din n+1 din n+2 din n+3 don't care transitioning data t wpre bank, col n notes 2 din n+4 din n+5 din n+6 din n+7 dqs, dqs# command address notes 3 notes 4 t wpst figure 4 2. write burst operation wl = 9 (al = cl-1, cwl = 5, bl8) nop write nop nop nop nop nop nop nop nop nop notes: 1. bl8, wl = 9; al = (cl - 1), cl = 5, cwl = 5. 2. din n = data-in from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0 = 00] or mr0[a1:0 = 01] and a12 = 1 during write command at t0. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 ck# ck dq al = 4 din n din n+1 din n+2 din n+3 don't care transitioning data t wpre bank, col n notes 2 notes 3 notes 4 dqs, dqs# address command cwl = 5 wl = al + cwl confidential - 67/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 4 3. write(bc4) to read (bc4) operation nop write nop nop nop nop nop nop nop nop read notes: 1. bc4, wl = 5, rl = 5. 2. din n = data-in from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[a1:0 = 10] during write command at t0 and read command at tn. 5. twtr controls the write to read delay to the same device and starts with the first rising clock edge after the last write data shown at t7. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 tn ck# ck dq din n din n+1 din n+2 din n+3 don't care transitioning data bank, col n notes 2 dqs, dqs# command address notes 3 notes 4 t wpst t wtr wl = 5 rl = 5 time break notes 5 t wpre figure 44 . write(bc4) to precharge operation nop write nop nop nop nop nop nop nop nop pre notes: 1. bc4, wl = 5, rl = 5. 2. din n = data-in from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[a1:0 = 10] during write command at t0. 5. the write recovery time (twr) referenced from the first rising clock edge after the last write data shown at t7. twr specifies the last burst write cycle until the precharge command can be issued to the same bank . t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 tn ck# ck dq din n din n+1 din n+2 din n+3 don't care transitioning data t wpre bank, col n notes 2 dqs, dqs# command address notes 3 notes 4 t wpst t wr wl = 5 time break notes 5 figure 45. write(bc4) otf to precharge operation nop write nop nop nop nop nop nop nop nop nop nop notes: 1. bc4 otf, wl = 5 (cwl = 5, al = 0) 2. din n (or b) = data-in from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 otf setting activated by mr0[a1:0 = 01] and a12 = 0 during write command at t0. 5. the write recovery time (twr) starts at the rising clock edge t9 (4 clocks from t5). t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck dq ta0 ta1 ta2 pre nop nop din n din n+1 din n+2 din n+3 don't care transitioning data bank col n valid 4 clocks t wr notes 3 notes 2 address notes 4 command dqs, dqs# t wpre t wpst time break wl = 5 notes 5 confidential - 68/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 46. write(bc8) to write(bc8) nop write nop nop write nop nop nop nop nop nop nop notes: 1. bl8, wl = 5 (cwl = 5, al = 0) 2. din n (or b) = data-in from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0 = 00] or mr0[a1:0 = 01] and a12 = 1 during write command at t0 and t4. 5. the write recovery time (twr) and write timing parameter (twtr) are referenced from the first rising clock edge after the last write data shown at t13. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck dq t12 t13 t14 nop nop nop din n din n+1 din n+2 din n+3 don't care transitioning data bank col n bank col b 4 clocks notes 3 notes 2 address notes 4 command dqs, dqs# t wpre t wpst t ccd din n+4 din n+5 din n+6 din n+7 din b din b+1 din b+2 din b+3 din b+4 din b+5 din b+6 din b+7 t wr t wtr wl = 5 wl = 5 figure 47. write(bc4) to write(bc4) otf nop write nop nop write nop nop nop nop nop nop nop notes: 1. bc4, wl = 5 (cwl = 5, al = 0) 2. din n (or b) = data-in from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[a1:0 = 01] and a12 = 0 during write command at t0 and t4. 5. the write recovery time (twr) and write timing parameter (twtr) are referenced from the first rising clock edge at t13 (4 clocks from t9). t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck dq t12 t13 t14 nop nop nop din n din n+1 din n+2 din n+3 don't care transitioning data bank col n bank col b 4 clocks notes 3 notes 2 address notes 4 command dqs, dqs# t wpre t wpst t ccd din b din b+1 din b+2 din b+3 t wr t wtr wl = 5 wl = 5 t wpst t wpre figure 48 . write(bc8) to read(bc4,bc8) otf nop write nop nop nop nop nop nop nop nop nop nop notes: 1. rl = 5 (cl = 5, al = 0), wl = 5 (cwl = 5, al = 0) 2. din n = data-in from column n; dout b = data-out from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0 = 00] or mr0[a1:0 = 01] and a12 = 1 during write command at t0. read command at t13 can be either bc4 or bl8 depending on mr0[a1:0] and a12 status at t13. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck dq t12 t13 t14 nop read nop din n din n+1 din n+2 din n+3 don't care transitioning data bank col n bank col b notes 3 notes 2 address notes 4 command dqs, dqs# t wpre din n+4 din n+5 din n+6 din n+7 rl = 5 t wtr wl = 5 t wpst confidential - 69/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 49 . write(bc4) to read(bc4,bc8) otf nop write nop nop nop nop nop nop nop nop nop nop notes: 1. rl = 5 (cl = 5, al = 0), wl = 5 (cwl =5, al = 0) 2. din n = data-in from column n; dout b = data-out from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[a1:0 = 01] and a12 = 0 during write command at t0. read command at t13 can be either bc4 or bl8 depending on a12 status at t13. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck dq t12 t13 t14 nop read nop din n din n+1 din n+2 din n+3 don't care transitioning data bank col n bank col b notes 3 notes 2 address notes 4 command dqs, dqs# t wpre rl = 5 t wtr wl = 5 t wpst 4 clocks figure 5 0. write(bc4) to read(bc4) nop write nop nop nop nop nop nop nop nop nop read notes: 1. rl = 5 (cl = 5, al = 0), wl = 5 (cwl =5, al = 0) 2. din n = data-in from column n; dout b = data-out from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[a1:0 = 10]. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck dq t12 t13 t14 nop nop nop din n din n+1 din n+2 din n+3 don't care transitioning data bank col n bank col b notes 3 notes 2 address notes 4 command dqs, dqs# t wpre rl = 5 t wtr wl = 5 t wpst figure 5 1. write(bc8) to write(bc4) otf nop write nop nop write nop nop nop nop nop nop nop notes: 1. wl = 5 (cwl = 5, al = 0) 2. din n (or b) = data-in from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0[a1:0 = 01] and a12 = 1 during write command at t0. bc4 setting activated by mr0[a1:0 = 01] and a12 = 0 during write command at t4. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck dq t12 t13 t14 nop nop nop din n din n+1 din n+2 din n+3 don't care transitioning data bank col n bank col b notes 3 notes 2 address notes 4 command dqs, dqs# t wpre din n+4 din n+5 din n+6 din n+7 t wtr wl = 5 t wpst t ccd t wr 4 clocks wl = 5 din b din b+1 din b+2 din b+3 confidential - 70/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 5 2. write(bc4) to write(bc8) otf nop write nop nop write nop nop nop nop nop nop nop notes: 1. wl = 5 (cwl = 5, al = 0) 2. din n (or b) = data-in from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[a1:0 = 01] and a12 = 0 during write command at t0. bl8 setting activated by mr0[a1:0 = 01] and a12 = 1 during write command at t4. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck dq t12 t13 t14 nop nop nop din n din n+1 din n+2 din n+3 don't care transitioning data bank col n bank col b 4 clocks notes 3 notes 2 address notes 4 command dqs, dqs# t wpre t wpst t ccd din b din b+1 din b+2 din b+3 t wr t wtr wl = 5 wl = 5 t wpst t wpre din b+4 din b+5 din b+6 din b+7 figure 5 3. refresh command timing nop ref nop ref nop nop valid valid valid valid valid ref notes: 1. only nop/des commands allowed after refresh command registered until trfc(min) expires. 2. time interval between two refresh commands may be extended to a maximum of 9 x trefi. t0 t1 ta0 ta1 tb0 tb1 tb2 tb3 tc0 ck# ck tc1 tc2 tc3 valid valid valid don't care transitioning data t rfc (min) command t rfc t refi (max. 9 * trefi) dram must be idle dram must be idle time break figure 54. self-refresh entry/exit timing ck# t1 t2 ta0 tb0 tc0 tc1 td0 teo t0 ck t cksre tf0 t ckesr t xs t xsdll nop sre nop valid nop valid valid odt cke command addr t is don't care time break notes: 1. only nop or des command. 2. valid commands not requiring a locked dll. 3. valid commands requiring a locked dll. t cksrx valid t cpded t is valid srx notes 1 notes 2 valid valid t rp odtl enter self refresh exit self refresh notes 3 confidential - 71/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 55 . active power-down entry and exit timing diagram ck# t1 t2 ta0 ta1 tb0 tb1 tc0 t0 ck cke nop valid nop nop nop nop valid t is t ih t is t ih valid valid valid valid t cke t pd t cpded t xp enter power-down mode exit power-down mode address command don't care time break note: valid command at t0 is act, nop, des or pre with still one bank remaining open after completion of the precharge command. figure 56. power-down entry after read and read with auto precharge nop rd or rda nop nop nop nop nop nop nop nop nop nop t0 t1 ta0 ta1 ta2 ta3 ta4 ta5 ta6 ta7 ta8 tb0 ck# ck tb1 valid din b din b+1 din b+2 din b+3 din b+4 din b+5 din b+6 din b+7 t pd t is rl = al + cl don't care transitioning data address cke t cpded valid valid valid command dqs, dqs# dq bl8 din b din b+1 din b+2 din b+3 dq bc4 t rdpden power - down entry time break confidential - 72/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 57 . power-down entry after write with auto precharge nop write nop nop nop nop nop nop nop nop nop nop t0 t1 ta0 ta1 ta2 ta3 ta4 ta5 ta6 ta7 tb0 tb1 ck# ck tb2 nop din b din b+1 din b+2 din b+3 din b+4 din b+5 din b+6 din b+7 wr t is wl = al + cwl don't care transitioning data cke t cpded valid bank, col n valid dq bl8 din b din b+1 din b+2 din b+3 dq bc4 t wrapden power - down entry time break tc0 tc1 nop valid a10 t pd notes: 1. wr is programmed through mr0. start internal precharge dqs, dqs# address command notes 1 figure 58 . power-down entry after write nop write nop nop nop nop nop nop nop nop nop nop t0 t1 ta0 ta1 ta2 ta3 ta4 ta5 ta6 ta7 tb0 tb1 ck# ck tb2 nop din b din b+1 din b+2 din b+3 din b+4 din b+5 din b+6 din b+7 t wr t is wl = al + cwl don't care transitioning data cke t cpded valid bank, col n valid dq bl8 din b din b+1 din b+2 din b+3 dq bc4 t wrpden power - down entry time break tc0 tc1 nop valid a10 t pd dqs, dqs# address command confidential - 73/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 59 . precharge power-down (fast exit mode) entry and exit ck# t1 t2 ta0 ta1 tb0 tb1 tc0 t0 ck cke nop valid nop nop nop nop valid t is t is t ih valid valid t cke t cpded enter power-down mode exit power-down mode command don't care time break t pd t xp figure 60. precharge power -down (slow exit mode) entry and exit ck# t1 t2 ta0 ta1 tb0 tb1 tc0 t0 ck cke nop valid nop nop nop nop valid t is t is t ih valid valid t cke t cpded enter power-down mode exit power-down mode command don't care time break t pd t xp td0 valid valid t xpdll confidential - 74/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 61 . refresh command to power-down entry ck# t1 t2 t3 ta0 ta1 t0 ck cke ref valid nop nop valid t is t pd valid t cpded don't care time break t refpden nop valid valid valid address command figure 62 . active command to power-down entry ck# t1 t2 t3 ta0 ta1 t0 ck cke active valid nop nop valid t is t pd valid t cpded don't care time break t actpden nop valid valid valid address command confidential - 75/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 63 . precharge, precharge all command to power-down entry ck# t1 t2 t3 ta0 ta1 t0 ck cke pre or prea valid nop nop valid t is t pd valid t cpded don't care time break t prepden nop valid valid valid address command figure 64 . mrs command to power-down entry ck# t1 ta0 ta1 tb0 tb1 t0 ck cke nop mrs nop valid t is t pd valid t cpded don't care time break t mrspden nop valid valid address command confidential - 76/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 65. synchronous odt timing example ( al = 3; cwl = 5; odtlon = al + cwl - 2 = 6 ; odtloff = al + cwl - 2 = 6 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck t12 t aon (min) odth4, min don't care transitioning data odt al = 3 t13 t14 cke t15 cwl - 2 odtloff = cwl + al - 2 odtlon = cwl + al - 2 dram_rtt t aon (max) t aof (min) t aof (max) rtt_nom al = 3 figure 66. synchronous odt example with bl = 4, wl = 7 nop nop nop nop nop nop nop wrs4 nop nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck t12 t13 t14 nop nop nop odth4 don't care transitioning data t15 nop odtloff = wl - 2 dram_rtt odt command cke t16 t17 nop nop odth4min odth4 odtlon = wl - 2 odtlon = wl - 2 odtloff = wl - 2 rtt_nom t aof (min) t aon (max) t aof (max) t aon (min) t aon (max) t aon (min) t aof (min) t aof (max) figure 67 . dynamic odt behavior with odt being asseted before and after the write nop nop nop nop wrs4 nop nop nop nop nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck t12 t13 t14 nop nop nop don't care transitioning data t15 nop odt t16 t17 nop nop odth4 odtlon valid rtt din n din n+1 din n+2 din n+3 dq odtloff t adc (min) t adc (max) t aon (min) odth4 odtlcwn4 t aon (max) rtt_nom rtt_wr t adc (min) t adc (max) t aof (min) t aof (max) rtt_nom odtlcnw wl notes: example for bc4 (via mrs or otf), al = 0, cwl = 5. odth4 applies to first registering odt high and to the registration of the write command. in this example, odth4 would be satisfied if odt went low at t8 (4 clocks after the write command). dqs, dqs# command address confidential - 77/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 68. dyn amic odt: behavior without write command, al = 0, cwl = 5 valid valid valid valid valid valid valid valid valid valid valid valid t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck don't care transitioning data odt odtloff odtlon rtt dq t aon (min) odth4 t aon (max) t adc (min) t adc (max) notes: 1. odth4 is defined from odt registered high to odt registered low, so in this example, odth4 is satisfied. 2. odt registered low at t5 would also be legal. rtt_nom dqs, dqs# address command figure 69. dynamic odt: behavior with odt pin being asserted together with write command for a duration of 6 clock cycles wrs8 nop nop nop nop nop nop nop nop nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck don't care transitioning data odt odtloff odtlcnw rtt dq t aon (min) odth8 t adc (max) t aof (min) t aof (max) notes: example for bl8 (via mrs or otf), al = 0, cwl = 5. in this example, odth8 = 6 is exactly satisfied. rtt_wr valid odtlon odtlcwn8 din b din b+1 din b+2 din b+3 dqs, dqs# address command din b+4 din b+5 din b+6 din b+7 wl confidential - 78/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 70. dynamic odt: behavior with odt pin being asserted together with write command for a duration of 6 clock cycles, example for bc4 (via mrs or otf), al = 0, cwl = 5. wrs4 nop nop nop nop nop nop nop nop nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck don't care transitioning data odt odtloff odtlcnw rtt dq t aon (min) odth4 t adc (max) t adc (min) t adc (max) notes: 1. odth4 is defined from odt registered high to odt registered low, so in this example, odth4 is satisfied. transitioning don f t care 2. odt registered low at t5 would also be legal. valid odtlon odtlcwn4 din n din n+1 din n+2 din n+3 dqs, dqs# address command wl rtt_wr t aof (min) t aof (max) rtt_nom figure 71. dynamic odt: behavior with odt pin being asserted together with write command for a duration of 4 clock cycles wrs4 nop nop nop nop nop nop nop nop nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck don't care transitioning data odt odtloff odtlcnw rtt dq t aon (min) odth4 t adc (max) t aof (min) t aof (max) notes: example for bc4 (via mrs or otf), al = 0, cwl = 5. in this example, odth4 = 4 is exactly satisfied. valid odtlon odtlcwn4 din n din n+1 din n+2 din n+3 dqs, dqs# address command wl rtt_wr confidential - 79/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 72. asynchronous odt timings on ddr3 sdram with fast odt transition t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck t12 t13 t14 don't care transitioning data t15 t16 t17 rtt t aonpd (min) t aonpd (max) t ih t is t aofpd (min) t aofpd (max) cke odt t ih t is rtt figure 73. synchronous to asynchronous transition during precharge power down (with dll frozen) entry (al = 0; cwl = 5; tanpd = wl - 1 = 4) ref nop nop nop nop nop nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck t12 don't care transitioning data rtt t rfc (min) t cpded (min) cke t aof (min) t aof (max) rtt odtloff t aofpd (min) rtt odtloff + t aofpd (max) odtloff + t aofpd (min) t aofpd (max) t aofpd (min) pd entry transition period t aofpd (max) rtt t13 ta0 ta1 ta2 ta3 t anpd rtt rtt command last sync. odt sync. or async. odt first async. odt time break figure 74. synchronous to asynchronous transition after refresh command (al = 0; cwl = 5; tanpd = wl - 1 = 4) ref nop nop nop nop nop nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck t12 don't care transitioning data rtt t rfc (min) t cpded (min) cke t aof (min) t aof (max) rtt odtloff t aofpd (min) rtt odtloff + t aofpd (max) odtloff + t aofpd (min) t aofpd (max) t aofpd (min) pd entry transition period t aofpd (max) rtt t13 ta0 ta1 ta2 ta3 t anpd rtt rtt command last sync. odt sync. or async. odt first async. odt time break confidential - 80/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 75. asynchronous to synchronous transition during precharge power down ( with dll frozen) exit (cl = 6; al = cl - 1; cwl = 5; tanpd = wl - 1 = 9) nop nop nop nop nop nop nop nop nop t0 t1 t2 ta0 ta1 ta2 ta3 ta4 ta5 ta6 tb0 tb1 ck# ck tb2 don't care transitioning data rtt t xpdll t anpd cke t aofpd (min) t aofpd (max) t aofpd (min) rtt odtloff + t aof (max) odtloff + t aof (min) t aofpd (max) t aof (min) pd exit transition period t aof (max) rtt tc0 tc1 tc2 td0 td1 rtt rtt rtt odtloff time break nop nop nop nop nop command last async. odt sync. or async. odt first sync. odt figure 76. transition period for short cke cycles, entry and exit period overlapping (al = 0, wl = 5, tanpd = wl - 1 = 4) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck# ck t12 t anpd don't care cke t13 t14 cke pd exit transition period nop ref nop nop nop nop nop nop nop nop nop nop nop nop nop t rfc (min) pd entry transition period t anpd t xpdll short cke low transition period command t anpd short cke high transition period t xpdll time break confidential - 81/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
figure 77. 78 -ball bga package 9x10.5x1.2mm(max) outline drawing information pin a1 index detail : "a" top view bottom view side view pin a1 index symbol d imension in inch dimension in mm min nom max min nom max a -- -- 0.047 -- -- 1.20 a1 0.012 -- 0.016 0.25 -- 0.40 d 0.350 0.354 0.358 8 .90 9 .00 9 .10 e 0.409 0.413 0.417 10.40 10.50 10.60 d1 -- 0.252 -- -- 6.40 -- e1 -- 0.378 -- -- 9.60 -- e -- 0.03 1 -- -- 0.80 -- b 0.016 0.018 0.020 0.40 0.45 0.50 confidential - 82/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3
alliance memory, inc. 511 taylor way, san carlos, ca 94070 tel: 650-610-6800 fax: 650-620-9211 www.alliancememory.com copyright ? alliance memory all rights reserved ? copyright 2007 alliance memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. part numbering system as4c 512m8d3 12 b a n dram 512m8=512mx8 d3= ddr3 12=800mhz b = fbga a =automotive ( - 40 c105 c) indicates pb and halogen free confidential - 83/83 - rev.1.0 june 2015 4gb auto-as4c512m8d3

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